Gwenhael Goavec-Merou 146617eae8 soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default		2024-06-18 22:14:24 +02:00
..
build	build/openfpgaloader: print command before executing it to ease debugging/manual tests.	2024-06-18 15:35:27 +02:00
compat
gen	litex/gen/common: Add short and long byte size definitions.	2024-06-13 09:54:20 +02:00
soc	soc/cores/cpu/zynq700/core.py: added csr into mem_map, added M_AXI_GP0 by default	2024-06-18 22:14:24 +02:00
tools	litex_json2dts_linux: Cleanup bootargs IP address generation.	2024-06-13 12:14:44 +02:00
__init__.py	get_data_mod(): fix recursive exception reporting	2024-04-22 12:09:45 +10:00