Florent Kermarrec 1ce48a973b clock/lattice_ecp5: Fix and rework 4-output solver implementation. ... The implementation was causing regressions on actual designs, rework done: - Only keep a common iteration loop as before. - Add iteration on CLKO dividers (to fall in the VCO range). - Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it. - If no feedback clock has been found: create it (if at least one free output available, if not raise an error).		2021-07-26 14:00:00 +02:00
..
__init__.py
test_axi.py
test_axi_lite.py
test_bitbang.py
test_clock.py	clock/lattice_ecp5: Fix and rework 4-output solver implementation.	2021-07-26 14:00:00 +02:00
test_code_8b10b.py	soc/cores/code_8b10b: add StreamEncoder/Decoder (to be used with LiteX's streams).	2020-10-21 09:29:21 +02:00
test_csr.py
test_ecc.py
test_emif.py
test_gearbox.py	inteconnect/stream: Increase io_lcm size when io_lcm/i_dw or io_lcm/o_dw < 2.	2021-03-18 13:47:10 +01:00
test_i2s.py
test_icap.py
test_packet.py
test_prbs.py
test_spi.py
test_spi_opi.py
test_stream.py
test_timer.py	test/test_timer: Update.	2021-05-27 19:37:51 +02:00
test_wishbone.py