Sebastien Bourdeauducq f62eff0309 bus/csr/Initiator: correct read latency		2013-07-27 15:37:47 +02:00
..
__init__.py	CSR bus definitions	2011-12-05 00:16:44 +01:00
csr.py	bus/csr/Initiator: correct read latency	2013-07-27 15:37:47 +02:00
dfi.py	dfi: split phase description	2013-07-10 19:56:47 +02:00
lasmibus.py	lasmibus: fix master locking	2013-07-15 21:45:07 +02:00
memory.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
transactions.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
wishbone.py	wishbone.py: add Crossbar (concurrent/parallel/many-to-many interconnect)	2013-07-22 10:30:44 +02:00
wishbone2csr.py	New migen.fhdl.std to simplify imports + len->flen	2013-05-22 17:11:09 +02:00
wishbone2lasmi.py	FSM: new API	2013-06-25 22:17:39 +02:00