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Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window: Before (delay = 0 taps): Write leveling: m0: |11000000000000011111111111| delay: 15 m1: |00000000000000111111111111| delay: 14 m2: |11110000000000000111111111| delay: 17 m3: |11110000000000000011111111| delay: 18 m4: |11111111110000000000000111| delay: 00 m5: |11111111110000000000000111| delay: 00 m6: |11111111111000000000000001| delay: 00 m7: |11111111111000000000000011| delay: 00 After (delay = 12 taps): Write leveling: m0: |11111111111111000000000000| delay: 00 m1: |11111111111100000000000001| delay: 00 m2: |00011111111111110000000000| delay: 03 m3: |00011111111111110000000000| delay: 03 m4: |00000000111111111111110000| delay: 08 m5: |00000000111111111111110000| delay: 08 m6: |00000000001111111111111000| delay: 10 m7: |00000000001111111111111000| delay: 10 |
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.. | ||
bios | ||
compiler_rt@81fb4f00c2 | ||
include | ||
libbase | ||
libcompiler_rt | ||
libnet | ||
common.mak | ||
mkmscimg.py |