123 lines
3.7 KiB
Python
123 lines
3.7 KiB
Python
# De0Nano-System On Chip / Generic Base for a Custom SOC
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# - Lm32 SoftCore
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# - 32MB Sdram
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# - 2KB Eeprom (TBD)
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# - G Sensor & AD Converter (TBD)
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# - Up to 72 GPIO (8 in/ 8 out)
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# - Uart
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# - Spi Slave & Master (Only Master)
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from fractions import Fraction
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from math import ceil
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from migen.fhdl.structure import *
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from migen.fhdl import verilog, autofragment
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from migen.bus import wishbone, csr, wishbone2csr, fml
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from soc import lm32, uart, rc5, gpio, spi_master, identifier, fmlbrg, hpdmc_sdr16
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from cmacros import get_macros
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from timings import *
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from constraints import Constraints
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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#Timings Param
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clk_freq = 50*MHz
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clk_period_ns = clk_freq*ns
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n = t2n(clk_period_ns)
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#==============================================================================
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# S O C
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#==============================================================================
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#
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# Configuration
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#===============================================================================
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# Csr
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csr_macros = get_macros("common/csrbase.h")
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def csr_offset(name):
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base = int(csr_macros[name + "_BASE"], 0)
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assert((base >= 0xe0000000) and (base <= 0xe0010000))
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return (base - 0xe0000000)//0x800
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# Interrupt
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interrupt_macros = get_macros("common/interrupt.h")
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def interrupt_n(name):
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return int(interrupt_macros[name + "_INTERRUPT"], 0)
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# Version
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version = get_macros("common/version.h")["VERSION"][1:-1]
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def get():
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#
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# Wishbone
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#===============================================================================
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cpu0 = lm32.LM32()
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wishbone2csr0 = wishbone2csr.WB2CSR()
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fmlbrg0 = fmlbrg.FMLBRG(16)
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hpdmc0 = hpdmc_sdr16.HPDMC_SDR16(13)
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# CSR 0x00000000 (shadow @0x80000000)
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# FML bridge 0x10000000 (shadow @0x90000000)
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wishbonecon = wishbone.InterconnectShared(
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[
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cpu0.ibus,
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cpu0.dbus
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], [
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(binc("000") , wishbone2csr0.wishbone),
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(binc("001") , fmlbrg0.wishbone)
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],
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register=True,
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offset=1)
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#
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# Fml
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#===============================================================================
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fmlcon0 = fml.Interconnect(fmlbrg0.fml,hpdmc0.fml)
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#
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# Csr
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#===============================================================================
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uart0 = uart.UART(csr_offset("UART"), clk_freq, baud=115200)
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identifier0 = identifier.Identifier(csr_offset("ID"), 0x1234, version, int(clk_freq))
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rc50 = rc5.RC5(csr_offset("RC5"),clk_freq)
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gpio0 = gpio.GPIO(csr_offset("GPIO"))
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led0 = gpio.GPIO(csr_offset("LED"))
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sw0 = gpio.GPIO(csr_offset("SW"),4)
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spi_master0 = spi_master.SPI_MASTER(csr_offset("SPI_MASTER"))
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csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
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uart0.csr,
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identifier0.bank.interface,
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rc50.csr,
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gpio0.csr,
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led0.csr,
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sw0.csr,
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spi_master0.csr,
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hpdmc0.csr
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])
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#
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# Interrupts
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#===============================================================================
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interrupts = Fragment([
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cpu0.interrupt[interrupt_n("UART")].eq(uart0.irq),
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cpu0.interrupt[interrupt_n("RC5")].eq(rc50.irq),
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cpu0.interrupt[interrupt_n("GPIO")].eq(gpio0.irq)
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])
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#
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# HouseKeeping
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#===============================================================================
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frag = autofragment.from_local() + interrupts
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cst = Constraints(uart0, rc50, gpio0, led0, sw0, spi_master0, hpdmc0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="soc",
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return_ns=True)
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src_qsf = cst.get_qsf(vns)
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return (src_verilog, src_qsf) |