litex/litex/soc
2020-02-11 16:44:25 +01:00
..
cores soc/add_cpu: simplify CPUNone integration 2020-02-10 17:40:46 +01:00
doc integration: svd: move svd generation to export 2020-02-04 23:49:08 +08:00
integration soc_core/soc_sdram: remove disclaimer (we'll add it later when designs will be adapted) 2020-02-11 16:44:25 +01:00
interconnect soc: integrate CSR master/interconnect/collection and IRQ collection 2020-02-07 19:50:35 +01:00
software bios/main: add LiteX tagline 2020-02-04 19:14:23 +01:00
__init__.py