litex/litex
Florent Kermarrec 1610a7f3fb bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
..
boards
build build/generic_platform: use list for sources instead of set 2018-07-20 10:01:33 +02:00
gen build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) 2018-05-01 12:02:54 +02:00
soc bios/sdram: fix read_level_scan result 2018-08-14 18:33:36 +02:00
__init__.py