111 lines
3.8 KiB
Python
111 lines
3.8 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.bank.description import CSRStorage, AutoCSR
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from migen.actorlib import dma_lasmi, structuring, sim, spi
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from milkymist.framebuffer.format import bpp, pixel_layout, FrameInitiator, VTG
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from milkymist.framebuffer.phy import Driver
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class Framebuffer(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi, lasmim, simulation=False):
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pack_factor = lasmim.dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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self._enable = CSRStorage()
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self.fi = FrameInitiator()
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self.dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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self.driver = Driver(pads_vga, pads_dvi)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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vtg = VTG()
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g = DataFlowGraph()
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g.add_connection(self.fi, vtg, sink_ep="timing")
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g.add_connection(self.dma, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(vtg, self.driver)
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self.submodules += CompositeActor(g)
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self.comb += [
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self.fi.trigger.eq(self._enable.storage),
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self.dma.generator.trigger.eq(self._enable.storage),
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]
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class Blender(PipelinedActor, AutoCSR):
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def __init__(self, nimages, latency):
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sink_layout = [("i"+str(i), pixel_layout) for i in range(nimages)]
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self.sink = Sink(sink_layout)
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self.source = Source(pixel_layout)
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factors = []
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for i in range(nimages):
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name = "f"+str(i)
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csr = CSRStorage(8, name=name)
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setattr(self, name, csr)
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factors.append(csr.storage)
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PipelinedActor.__init__(self, latency)
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###
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sink_registered = Record(sink_layout)
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self.sync += If(self.pipe_ce, sink_registered.eq(self.sink.payload))
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imgs = [getattr(sink_registered, "i"+str(i)) for i in range(nimages)]
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outval = Record(pixel_layout)
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for e in pixel_layout:
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name = e[0]
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inpixs = [getattr(img, name) for img in imgs]
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outpix = getattr(outval, name)
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for component in ["r", "g", "b"]:
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incomps = [getattr(pix, component) for pix in inpixs]
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outcomp = getattr(outpix, component)
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outcomp_full = Signal(19)
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self.comb += [
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outcomp_full.eq(sum(incomp*factor for incomp, factor in zip(incomps, factors))),
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If(outcomp_full[18],
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outcomp.eq(2**10 - 1) # saturate on overflow
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).Else(
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outcomp.eq(outcomp_full[8:18])
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)
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]
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pipe_stmts = []
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for i in range(latency-1):
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new_outval = Record(pixel_layout)
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pipe_stmts.append(new_outval.eq(outval))
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outval = new_outval
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self.sync += If(self.pipe_ce, pipe_stmts)
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self.comb += self.source.payload.eq(outval)
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class MixFramebuffer(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi, *lasmims, blender_latency=5):
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pack_factor = lasmims[0].dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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self._enable = CSRStorage()
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self.fi = FrameInitiator()
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self.blender = Blender(len(lasmims), blender_latency)
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self.driver = Driver(pads_vga, pads_dvi)
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self.comb += self.fi.trigger.eq(self._enable.storage)
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g = DataFlowGraph()
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for n, lasmim in enumerate(lasmims):
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dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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g.add_connection(dma, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)])
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self.comb += dma.generator.trigger.eq(self._enable.storage)
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setattr(self, "dma"+str(n), dma)
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vtg = VTG()
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g.add_connection(self.fi, vtg, sink_ep="timing")
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g.add_connection(self.blender, vtg, sink_ep="pixels")
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g.add_connection(vtg, self.driver)
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self.submodules += CompositeActor(g)
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