Sebastien Bourdeauducq 17b2588321 ddrphy: reads OK, write data coming out 1/2 cycle too late		2012-02-24 15:05:52 +01:00
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bios	ddrphy: reads OK, write data coming out 1/2 cycle too late	2012-02-24 15:05:52 +01:00
include	dfii: new design	2012-02-23 21:21:07 +01:00
libbase	libbase: blocking UART write if IRQs are enabled	2012-02-07 15:12:27 +01:00
libextra	software: shell from original BIOS	2012-02-07 15:02:44 +01:00
include.mak	software: enable -Wmissing-prototypes	2012-02-07 13:02:06 +01:00