17 lines
460 B
Python
17 lines
460 B
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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from migen.genlib.divider import Divider
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class CDM(Module):
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def __init__(self):
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self.submodules.divider = Divider(5)
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self.clock_domains.cd_sys = ClockDomain(reset_less=True)
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class MultiMod(Module):
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def __init__(self):
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self.submodules.foo = CDM()
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self.submodules.bar = CDM()
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mm = MultiMod()
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print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
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