15 lines
492 B
Python
15 lines
492 B
Python
from migen.fhdl.std import *
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self):
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self.specials.mem = Memory(32, 100, init=[5, 18, 32])
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p1 = self.mem.get_port(write_capable=True, we_granularity=8)
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p2 = self.mem.get_port(has_re=True, clock_domain="rd")
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self.specials += p1, p2
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self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
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p2.adr, p2.dat_r, p2.re}
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example = Example()
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print(verilog.convert(example, example.ios))
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