37 lines
1.1 KiB
Python
37 lines
1.1 KiB
Python
from migen.fhdl.std import *
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from migen.sim.generic import run_simulation
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# A slightly more elaborate counter.
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# Has a clock enable (CE) signal, counts on more bits
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# and resets with a negative number.
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class Counter(Module):
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def __init__(self):
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self.ce = Signal()
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# Demonstrate negative numbers and signals larger than 32 bits.
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self.count = Signal((37, True), reset=-5)
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self.sync += If(self.ce, self.count.eq(self.count + 1))
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def do_simulation(self, selfp):
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# Only assert CE every second cycle.
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# => each counter value is held for two cycles.
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if selfp.simulator.cycle_counter % 2:
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selfp.ce = 0 # This is how you write to a signal.
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else:
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selfp.ce = 1
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print("Cycle: " + str(selfp.simulator.cycle_counter) + " Count: " + \
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str(selfp.count))
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# Output is:
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# Cycle: 0 Count: -5
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# Cycle: 1 Count: -5
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# Cycle: 2 Count: -4
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# Cycle: 3 Count: -4
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# Cycle: 4 Count: -3
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# ...
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if __name__ == "__main__":
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dut = Counter()
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# Demonstrate VCD output
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run_simulation(dut, vcd_name="my.vcd", ncycles=20)
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