52 lines
1.4 KiB
Python
52 lines
1.4 KiB
Python
# Copyright (C) 2012 Vermeer Manufacturing Co.
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# License: GPLv3 with additional permissions (see README).
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from migen.fhdl.structure import *
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from migen.sim.generic import Simulator, TopLevel
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# A slightly improved counter.
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# Has a clock enable (CE) signal, counts on more bits
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# and resets with a negative number.
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class Counter:
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def __init__(self):
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self.ce = Signal()
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# Demonstrate negative numbers and signals larger than 32 bits.
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self.count = Signal((37, True), reset=-5)
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def do_simulation(self, s):
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# Only assert CE every second cycle.
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# => each counter value is held for two cycles.
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if s.cycle_counter % 2:
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s.wr(self.ce, 0) # This is how you write to a signal.
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else:
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s.wr(self.ce, 1)
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print("Cycle: " + str(s.cycle_counter) + " Count: " + \
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str(s.rd(self.count)))
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# Set the "initialize" property on our simulation function.
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# The simulator will call it during the reset cycle,
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# with s.cycle_counter == -1.
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do_simulation.initialize = True
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# Output is:
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# Cycle: -1 Count: 0
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# Cycle: 0 Count: -5
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# Cycle: 1 Count: -5
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# Cycle: 2 Count: -4
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# Cycle: 3 Count: -4
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# Cycle: 4 Count: -3
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# ...
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def get_fragment(self):
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sync = [If(self.ce, self.count.eq(self.count + 1))]
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sim = [self.do_simulation]
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return Fragment(sync=sync, sim=sim)
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def main():
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dut = Counter()
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# Instantiating the generic top-level ourselves lets us
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# specify a VCD output file.
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sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
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sim.run(20)
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main()
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