158 lines
4.7 KiB
Python
158 lines
4.7 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.fhdl.tracer import get_obj_var_name
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class _Register(HUID):
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def __init__(self, name):
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HUID.__init__(self)
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self.name = get_obj_var_name(name)
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if self.name is None:
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raise ValueError("Cannot extract register name from code, need to specify.")
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if len(self.name) > 2 and self.name[:2] == "r_":
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self.name = self.name[2:]
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class RegisterRaw(_Register):
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def __init__(self, size=1, name=None):
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_Register.__init__(self, name)
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self.size = size
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self.re = Signal()
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self.r = Signal(self.size)
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self.w = Signal(self.size)
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(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
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class Field:
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def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
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self.name = get_obj_var_name(name)
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if self.name is None:
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raise ValueError("Cannot extract field name from code, need to specify.")
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self.size = size
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self.access_bus = access_bus
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self.access_dev = access_dev
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self.storage = Signal(self.size, reset=reset)
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self.atomic_write = atomic_write
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if self.access_bus == READ_ONLY and self.access_dev == WRITE_ONLY:
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self.w = Signal(self.size)
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else:
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if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
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self.r = Signal(self.size, reset=reset)
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if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
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self.w = Signal(self.size)
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self.we = Signal()
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class RegisterFields(_Register):
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def __init__(self, *fields, name=None):
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_Register.__init__(self, name)
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self.fields = fields
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class RegisterField(RegisterFields):
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def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
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self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="")
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RegisterFields.__init__(self, self.field, name=name)
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def regprefix(prefix, registers):
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for register in registers:
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register.name = prefix + register.name
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def memprefix(prefix, memories):
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for memory in memories:
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memory.name_override = prefix + memory.name_override
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class AutoReg:
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def get_memories(self):
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r = []
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for k, v in self.__dict__.items():
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if isinstance(v, Memory):
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r.append(v)
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elif hasattr(v, "get_memories") and callable(v.get_memories):
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memories = v.get_memories()
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memprefix(k + "_", memories)
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r += memories
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return sorted(r, key=lambda x: x.huid)
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def get_registers(self):
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r = []
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for k, v in self.__dict__.items():
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if isinstance(v, _Register):
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r.append(v)
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elif hasattr(v, "get_registers") and callable(v.get_registers):
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registers = v.get_registers()
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regprefix(k + "_", registers)
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r += registers
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return sorted(r, key=lambda x: x.huid)
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(ALIAS_NON_ATOMIC, ALIAS_ATOMIC_HOLD, ALIAS_ATOMIC_COMMIT) = range(3)
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class FieldAlias:
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def __init__(self, mode, f, start, end, commit_list):
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self.mode = mode
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self.size = end - start
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self.access_bus = f.access_bus
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self.access_dev = f.access_dev
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if mode == ALIAS_ATOMIC_HOLD:
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self.storage = Signal(end-start, name="atomic_hold")
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self.commit_to = f.storage[start:end]
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else:
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self.storage = f.storage[start:end]
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if mode == ALIAS_ATOMIC_COMMIT:
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self.commit_list = commit_list
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else:
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self.commit_list = []
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# device access is through the original field
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def expand_description(description, busword):
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d = []
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for reg in description:
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if isinstance(reg, RegisterRaw):
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if reg.size > busword:
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raise ValueError("Raw register larger than a bus word")
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d.append(reg)
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elif isinstance(reg, RegisterFields):
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f = []
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offset = 0
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totalsize = 0
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for field in reg.fields:
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offset += field.size
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totalsize += field.size
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if offset > busword:
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# add padding
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padding = busword - (totalsize % busword)
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if padding != busword:
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totalsize += padding
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offset += padding
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top = field.size
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commit_list = []
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while offset > busword:
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if field.atomic_write:
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if offset - busword > busword:
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mode = ALIAS_ATOMIC_HOLD
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else:
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# last iteration
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mode = ALIAS_ATOMIC_COMMIT
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else:
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mode = ALIAS_NON_ATOMIC
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slice1 = busword - offset + top
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slice2 = min(offset - busword, busword)
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if slice1:
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alias = FieldAlias(mode, field, top - slice1, top, commit_list)
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f.append(alias)
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if mode == ALIAS_ATOMIC_HOLD:
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commit_list.append(alias)
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top -= slice1
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d.append(RegisterFields(*f, name=reg.name))
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alias = FieldAlias(mode, field, top - slice2, top, commit_list)
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f = [alias]
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if mode == ALIAS_ATOMIC_HOLD:
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commit_list.append(alias)
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top -= slice2
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offset -= busword
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else:
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f.append(field)
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if f:
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d.append(RegisterFields(*f, name=reg.name))
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else:
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raise TypeError
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return d
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