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litex/migen/fhdl
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Sebastien Bourdeauducq e1702c422c introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
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__init__.py Initial import, FHDL basic structure, divider example 2011-12-04 16:44:38 +01:00
bitcontainer.py migen/fhdl/bitcontainer: fix signed arrays (map is an iterator) 2013-12-10 23:32:12 +01:00
conv_output.py introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
decorators.py decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
edif.py introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
module.py fhdl/visit: fix TransformModule 2015-03-14 17:45:11 +01:00
namer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
simplify.py fhdl/decorators: make the transform logic more idiomatic 2015-04-04 19:16:50 +08:00
specials.py introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
std.py decorators: fix stacklevel, export in std 2015-04-05 18:47:45 +08:00
structure.py Raise exception when not using correct boolean operators 2014-10-27 19:40:22 +08:00
tools.py fhdl/tools: do not attempt to rename sync clock domain if it does not exist 2014-11-21 14:51:05 -08:00
tracer.py remove trailing whitespaces 2014-10-17 17:08:46 +08:00
verilog.py introduce conversion output object (prevents file IO in FHDL backends) 2015-04-08 20:28:23 +08:00
visit.py fhdl/visit: remove TransformModule 2015-04-04 20:12:22 +08:00