139 lines
2.5 KiB
Verilog
139 lines
2.5 KiB
Verilog
module minimac3(
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input sys_clk,
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input sys_rst,
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/* Control */
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input rx_ready_0,
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output rx_done_0,
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output [10:0] rx_count_0,
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input rx_ready_1,
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output rx_done_1,
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output [10:0] rx_count_1,
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input tx_start,
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output tx_done,
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input [10:0] tx_count,
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/* WISHBONE to access RAM */
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input [29:0] wb_adr_i,
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output [31:0] wb_dat_o,
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input [31:0] wb_dat_i,
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input [3:0] wb_sel_i,
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input wb_stb_i,
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input wb_cyc_i,
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output wb_ack_o,
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input wb_we_i,
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/* To PHY */
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input phy_tx_clk,
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output [3:0] phy_tx_data,
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output phy_tx_en,
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output phy_tx_er,
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input phy_rx_clk,
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input [3:0] phy_rx_data,
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input phy_dv,
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input phy_rx_er,
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input phy_col,
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input phy_crs
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);
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wire [1:0] phy_rx_ready;
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wire [1:0] phy_rx_done;
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wire [10:0] phy_rx_count_0;
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wire [10:0] phy_rx_count_1;
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wire phy_tx_start;
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wire phy_tx_done;
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wire [10:0] phy_tx_count;
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minimac3_sync sync(
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.sys_clk(sys_clk),
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.phy_rx_clk(phy_rx_clk),
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.phy_tx_clk(phy_tx_clk),
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.sys_rx_ready({rx_ready_1, rx_ready_0}),
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.sys_rx_done({rx_done_1, rx_done_0}),
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.sys_rx_count_0(rx_count_0),
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.sys_rx_count_1(rx_count_1),
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.sys_tx_start(tx_start),
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.sys_tx_done(tx_done),
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.sys_tx_count(tx_count),
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.phy_rx_ready(phy_rx_ready),
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.phy_rx_done(phy_rx_done),
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.phy_rx_count_0(phy_rx_count_0),
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.phy_rx_count_1(phy_rx_count_1),
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.phy_tx_start(phy_tx_start),
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.phy_tx_done(phy_tx_done),
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.phy_tx_count(phy_tx_count)
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);
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wire [7:0] rxb0_dat;
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wire [10:0] rxb0_adr;
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wire rxb0_we;
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wire [7:0] rxb1_dat;
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wire [10:0] rxb1_adr;
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wire rxb1_we;
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wire [7:0] txb_dat;
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wire [10:0] txb_adr;
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minimac3_memory memory(
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.sys_clk(sys_clk),
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.sys_rst(sys_rst),
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.phy_rx_clk(phy_rx_clk),
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.phy_tx_clk(phy_tx_clk),
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.wb_adr_i(wb_adr_i),
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.wb_dat_o(wb_dat_o),
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.wb_dat_i(wb_dat_i),
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.wb_sel_i(wb_sel_i),
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.wb_stb_i(wb_stb_i),
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.wb_cyc_i(wb_cyc_i),
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.wb_ack_o(wb_ack_o),
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.wb_we_i(wb_we_i),
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.rxb0_dat(rxb0_dat),
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.rxb0_adr(rxb0_adr),
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.rxb0_we(rxb0_we),
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.rxb1_dat(rxb1_dat),
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.rxb1_adr(rxb1_adr),
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.rxb1_we(rxb1_we),
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.txb_dat(txb_dat),
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.txb_adr(txb_adr)
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);
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minimac3_tx tx(
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.phy_tx_clk(phy_tx_clk),
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.tx_start(phy_tx_start),
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.tx_done(phy_tx_done),
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.tx_count(phy_tx_count),
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.txb_dat(txb_dat),
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.txb_adr(txb_adr),
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.phy_tx_en(phy_tx_en),
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.phy_tx_data(phy_tx_data)
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);
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assign phy_tx_er = 1'b0;
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minimac3_rx rx(
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.phy_rx_clk(phy_rx_clk),
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.rx_ready(phy_rx_ready),
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.rx_done(phy_rx_done),
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.rx_count_0(phy_rx_count_0),
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.rx_count_1(phy_rx_count_1),
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.rxb0_dat(rxb0_dat),
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.rxb0_adr(rxb0_adr),
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.rxb0_we(rxb0_we),
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.rxb1_dat(rxb1_dat),
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.rxb1_adr(rxb1_adr),
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.rxb1_we(rxb1_we),
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.phy_dv(phy_dv),
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.phy_rx_data(phy_rx_data),
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.phy_rx_er(phy_rx_er)
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);
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endmodule
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