Florent Kermarrec 1f6983da2c soc/cores/liteeth_mini: add phy model for verilator simulation		2015-11-11 14:22:27 +01:00
..
cpu	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
flash	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
liteeth_mini	soc/cores/liteeth_mini: add phy model for verilator simulation	2015-11-11 14:22:27 +01:00
sdram	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
spi	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
uart	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
__init__.py	litex: reorganize things, first work working version	2015-11-07 17:48:55 +01:00
gpio.py	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
identifier.py	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00
timer.py	avoid forking migen, we will add custom modules in litex/gen but will use upstream migen for common modules	2015-11-11 12:10:55 +01:00