Sebastien Bourdeauducq 1a845d4553 32-device, 8-bit CSR bus		2011-12-17 15:54:49 +01:00
..
bank	32-device, 8-bit CSR bus	2011-12-17 15:54:49 +01:00
bus	32-device, 8-bit CSR bus	2011-12-17 15:54:49 +01:00
corelogic	fhdl: simpler syntax	2011-12-16 21:30:14 +01:00
fhdl	verilog: get the simulator to run the combinatorial process at the beginning	2011-12-17 15:20:22 +01:00
__init__.py	Initial import, FHDL basic structure, divider example	2011-12-04 16:44:38 +01:00