litex/build
Florent Kermarrec 79dbb6da4b replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows) 2015-01-19 09:45:34 +01:00
..
.keep_me replace Makefile with make.py (will enable verilog rtl generation for integration with standard flows) 2015-01-19 09:45:34 +01:00