189 lines
6.8 KiB
Python
189 lines
6.8 KiB
Python
from misoclib.mem.litesata.common import *
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from migen.genlib.cdc import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.bank.description import *
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from misoclib.soc import SoC
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from misoclib.tools.litescope.common import *
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from misoclib.tools.litescope.frontend.la import LiteScopeLA
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from misoclib.tools.litescope.core.port import LiteScopeTerm
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from misoclib.com.uart.bridge import UARTWishboneBridge
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from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.phy import LiteSATAPHY
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from misoclib.mem.litesata.core import LiteSATACore
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from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
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from misoclib.mem.litesata.frontend.bist import LiteSATABIST
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class _CRG(Module):
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def __init__(self, platform):
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self.clock_domains.cd_sys = ClockDomain()
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clk200 = platform.request("clk200")
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clk200_se = Signal()
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self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
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pll_locked = Signal()
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pll_fb = Signal()
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pll_sys = Signal()
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self.specials += [
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Instance("PLLE2_BASE",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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# VCO @ 1GHz
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
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p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
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i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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# 166MHz
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p_CLKOUT0_DIVIDE=6, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
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p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
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p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
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p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
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p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
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),
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Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset")),
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]
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class BISTLeds(Module):
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def __init__(self, platform, sata_phys):
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for i, sata_phy in enumerate(sata_phys):
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# 1Hz blinking leds (sata_rx and sata_tx clocks)
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rx_led = platform.request("user_led", 2*i)
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rx_cnt = Signal(32)
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freq = int(frequencies[sata_phy.revision]*1000*1000)
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self.sync.sata_rx += \
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If(rx_cnt == 0,
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rx_led.eq(~rx_led),
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rx_cnt.eq(freq//2)
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).Else(
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rx_cnt.eq(rx_cnt-1)
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)
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# ready leds
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self.comb += platform.request("user_led", 2*i+1).eq(sata_phy.ctrl.ready)
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class BISTSoC(SoC, AutoCSR):
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default_platform = "kc705"
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csr_map = {
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"sata_bist": 16
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}
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csr_map.update(SoC.csr_map)
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def __init__(self, platform):
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clk_freq = 166*1000000
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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self.submodules.crg = _CRG(platform)
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# SATA PHY/Core/Frontend
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self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq)
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self.submodules.sata_core = LiteSATACore(self.sata_phy)
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self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
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self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
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# Status Leds
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self.submodules.leds = BISTLeds(platform, [self.sata_phy])
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platform.add_platform_command("""
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create_clock -name sys_clk -period 6 [get_nets sys_clk]
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create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
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create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
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set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
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set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
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set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
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""")
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class BISTSoCDevel(BISTSoC, AutoCSR):
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csr_map = {
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"la": 17
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}
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csr_map.update(BISTSoC.csr_map)
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def __init__(self, platform):
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BISTSoC.__init__(self, platform)
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self.sata_core_link_rx_fsm_state = Signal(4)
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self.sata_core_link_tx_fsm_state = Signal(4)
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self.sata_core_transport_rx_fsm_state = Signal(4)
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self.sata_core_transport_tx_fsm_state = Signal(4)
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self.sata_core_command_rx_fsm_state = Signal(4)
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self.sata_core_command_tx_fsm_state = Signal(4)
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debug = (
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self.sata_phy.ctrl.ready,
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self.sata_phy.source.stb,
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self.sata_phy.source.data,
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self.sata_phy.source.charisk,
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self.sata_phy.sink.stb,
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self.sata_phy.sink.data,
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self.sata_phy.sink.charisk,
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self.sata.core.command.sink.stb,
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self.sata.core.command.sink.sop,
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self.sata.core.command.sink.eop,
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self.sata.core.command.sink.ack,
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self.sata.core.command.sink.write,
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self.sata.core.command.sink.read,
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self.sata.core.command.sink.identify,
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self.sata.core.command.source.stb,
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self.sata.core.command.source.sop,
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self.sata.core.command.source.eop,
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self.sata.core.command.source.ack,
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self.sata.core.command.source.write,
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self.sata.core.command.source.read,
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self.sata.core.command.source.identify,
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self.sata.core.command.source.failed,
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self.sata.core.command.source.data,
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self.sata_core_link_rx_fsm_state,
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self.sata_core_link_tx_fsm_state,
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self.sata_core_transport_rx_fsm_state,
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self.sata_core_transport_tx_fsm_state,
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self.sata_core_command_rx_fsm_state,
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self.sata_core_command_tx_fsm_state,
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)
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self.submodules.la = LiteScopeLA(debug, 2048)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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def do_finalize(self):
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BISTSoC.do_finalize(self)
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self.comb += [
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self.sata_core_link_rx_fsm_state.eq(self.sata.core.link.rx.fsm.state),
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self.sata_core_link_tx_fsm_state.eq(self.sata.core.link.tx.fsm.state),
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self.sata_core_transport_rx_fsm_state.eq(self.sata.core.transport.rx.fsm.state),
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self.sata_core_transport_tx_fsm_state.eq(self.sata.core.transport.tx.fsm.state),
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self.sata_core_command_rx_fsm_state.eq(self.sata.core.command.rx.fsm.state),
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self.sata_core_command_tx_fsm_state.eq(self.sata.core.command.tx.fsm.state)
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]
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def do_exit(self, vns):
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self.la.export(vns, "test/la.csv")
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default_subtarget = BISTSoC
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