69 lines
2.3 KiB
Python
69 lines
2.3 KiB
Python
from misoclib.mem.litesata.common import *
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from misoclib.mem.litesata.core import LiteSATACore
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from misoclib.mem.litesata.frontend.common import *
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from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
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from misoclib.mem.litesata.frontend.bist import LiteSATABISTGenerator, LiteSATABISTChecker
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from misoclib.mem.litesata.frontend.striping import LiteSATAStriping
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from misoclib.mem.litesata.test.common import *
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from misoclib.mem.litesata.test.model.hdd import *
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class TB(Module):
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def __init__(self):
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self.submodules.hdd0 = HDD(n=0,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.submodules.core0 = LiteSATACore(self.hdd0.phy)
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self.submodules.hdd1 = HDD(n=1,
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link_debug=False, link_random_level=0,
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transport_debug=False, transport_loopback=False,
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hdd_debug=True)
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self.submodules.core1 = LiteSATACore(self.hdd1.phy)
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self.submodules.striping = LiteSATAStriping([self.core0, self.core1])
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self.submodules.crossbar = LiteSATACrossbar(self.striping)
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self.submodules.generator = LiteSATABISTGenerator(self.crossbar.get_port())
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self.submodules.checker = LiteSATABISTChecker(self.crossbar.get_port())
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def gen_simulation(self, selfp):
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hdd0 = self.hdd0
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hdd0.malloc(0, 64)
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hdd1 = self.hdd1
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hdd1.malloc(0, 64)
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sector = 0
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count = 1
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generator = selfp.generator
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checker = selfp.checker
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while True:
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# write data
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generator.sector = sector
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generator.count = count
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generator.start = 1
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yield
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generator.start = 0
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yield
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while generator.done == 0:
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yield
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# verify data
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checker.sector = sector
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checker.count = count
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checker.start = 1
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yield
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checker.start = 0
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yield
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while checker.done == 0:
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yield
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print("errors {}".format(checker.errors))
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# prepare next iteration
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sector += 1
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count = max((count + 1)%8, 1)
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if __name__ == "__main__":
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run_simulation(TB(), ncycles=8192*2, vcd_name="my.vcd", keep_files=True)
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