170 lines
2.9 KiB
C
170 lines
2.9 KiB
C
#include <generated/csr.h>
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#ifdef DFII_BASE
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#include <stdio.h>
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#include <stdlib.h>
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#include <generated/sdram_phy.h>
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#include <generated/mem.h>
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#include <hw/flags.h>
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#include "sdram.h"
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static void cdelay(int i)
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{
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while(i > 0) {
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#if defined (__lm32__)
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__asm__ volatile("nop");
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#elif defined (__or1k__)
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__asm__ volatile("l.nop");
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#else
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#error Unsupported architecture
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#endif
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i--;
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}
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}
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void ddrsw(void)
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{
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dfii_control_write(DFII_CONTROL_CKE);
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printf("DDR now under software control\n");
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}
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void ddrhw(void)
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{
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dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
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printf("DDR now under hardware control\n");
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}
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void ddrrow(char *_row)
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{
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char *c;
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unsigned int row;
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if(*_row == 0) {
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dfii_pi0_address_write(0x0000);
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dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(15);
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printf("Precharged\n");
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} else {
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row = strtoul(_row, &c, 0);
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if(*c != 0) {
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printf("incorrect row\n");
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return;
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}
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dfii_pi0_address_write(row);
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dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CS);
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cdelay(15);
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printf("Activated row %d\n", row);
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}
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}
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void ddrrd(char *startaddr)
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{
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char *c;
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unsigned int addr;
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int i;
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if(*startaddr == 0) {
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printf("ddrrd <address>\n");
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return;
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}
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addr = strtoul(startaddr, &c, 0);
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if(*c != 0) {
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printf("incorrect address\n");
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return;
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}
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dfii_pird_address_write(addr);
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dfii_pird_baddress_write(0);
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command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA);
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cdelay(15);
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for(i=0;i<8;i++)
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printf("%02x", MMPTR(0xe0001038+4*i));
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for(i=0;i<8;i++)
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printf("%02x", MMPTR(0xe000108c+4*i));
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printf("\n");
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}
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void ddrwr(char *startaddr)
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{
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char *c;
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unsigned int addr;
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int i;
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if(*startaddr == 0) {
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printf("ddrrd <address>\n");
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return;
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}
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addr = strtoul(startaddr, &c, 0);
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if(*c != 0) {
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printf("incorrect address\n");
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return;
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}
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for(i=0;i<8;i++) {
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MMPTR(0xe0001018+4*i) = i;
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MMPTR(0xe000106c+4*i) = 0xf0 + i;
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}
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dfii_piwr_address_write(addr);
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dfii_piwr_baddress_write(0);
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command_pwr(DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS|DFII_COMMAND_WRDATA);
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}
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#define TEST_SIZE (4*1024*1024)
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int memtest_silent(void)
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{
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volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
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int i;
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unsigned int prv;
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unsigned int error_cnt;
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prv = 0;
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for(i=0;i<TEST_SIZE/4;i++) {
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prv = 1664525*prv + 1013904223;
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array[i] = prv;
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}
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prv = 0;
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error_cnt = 0;
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for(i=0;i<TEST_SIZE/4;i++) {
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prv = 1664525*prv + 1013904223;
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if(array[i] != prv)
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error_cnt++;
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}
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return error_cnt;
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}
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int memtest(void)
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{
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unsigned int e;
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e = memtest_silent();
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if(e != 0) {
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printf("Memtest failed: %d/%d words incorrect\n", e, TEST_SIZE/4);
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return 0;
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} else {
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printf("Memtest OK\n");
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return 1;
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}
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}
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int ddrinit(void)
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{
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printf("Initializing DDR SDRAM...\n");
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init_sequence();
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dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
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if(!memtest())
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return 0;
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return 1;
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}
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#endif
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