52 lines
1.6 KiB
Python
52 lines
1.6 KiB
Python
from migen.fhdl.std import *
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from migen.flow.actor import Sink, Source
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from lib.sata.k7sataphy.std import *
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from lib.sata.k7sataphy.gtx import K7SATAPHYGTX, K7SATAPHYRXAlign
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from lib.sata.k7sataphy.gtx import K7SATAPHYRXConvert, K7SATAPHYTXConvert
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from lib.sata.k7sataphy.clocking import K7SATAPHYClocking
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from lib.sata.k7sataphy.ctrl import K7SATAPHYHostCtrl, K7SATAPHYDeviceCtrl
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class K7SATAPHY(Module):
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def __init__(self, pads, host=True):
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self.sink = Sink([("d", 32)], True)
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self.source = Source([("d", 32)], True)
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gtx = K7SATAPHYGTX(pads, "SATA3")
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clocking = K7SATAPHYClocking(pads, gtx)
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rxalign = K7SATAPHYRXAlign()
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rxconvert = K7SATAPHYRXConvert()
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txconvert = K7SATAPHYTXConvert()
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self.submodules += gtx, clocking, rxalign, rxconvert, txconvert
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self.comb += [
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rxalign.rxdata_i.eq(gtx.rxdata),
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rxalign.rxcharisk_i.eq(gtx.rxcharisk),
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rxconvert.rxdata.eq(rxalign.rxdata_o),
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rxconvert.rxcharisk.eq(rxalign.rxcharisk_o),
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gtx.txdata.eq(txconvert.txdata),
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gtx.txcharisk.eq(txconvert.txcharisk)
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]
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if host:
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ctrl = K7SATAPHYHostCtrl(gtx)
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else:
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ctrl = K7SATAPHYDeviceCtrl(gtx)
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self.submodules += ctrl
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self.comb += [
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If(ctrl.link_up,
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txconvert.sink.stb.eq(self.sink.stb),
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txconvert.sink.data.eq(self.sink.d),
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txconvert.sink.charisk.eq(0),
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self.sink.ack.eq(txconvert.sink.ack),
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).Else(
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txconvert.sink.stb.eq(1),
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txconvert.sink.data.eq(ctrl.txdata),
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txconvert.sink.charisk.eq(ctrl.txcharisk)
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),
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self.source.stb.eq(rxconvert.source.stb),
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self.source.payload.eq(rxconvert.source.payload),
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rxconvert.source.ack.eq(self.source.ack),
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ctrl.rxdata.eq(rxconvert.source.data)
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]
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