488 lines
18 KiB
Python
488 lines
18 KiB
Python
# 1:2 and 1:4 frequency-ratio DDR / LPDDR / DDR2 / DDR3 PHYs for Spartan-6
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#
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# Assert dfi_wrdata_en and present the data
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# on dfi_wrdata_mask/dfi_wrdata in the same
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# cycle as the write command.
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#
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# Assert dfi_rddata_en in the same cycle as the read
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# command. The data will come back on dfi_rddata
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# 5 cycles later, along with the assertion
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# of dfi_rddata_valid.
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#
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# This PHY only supports CAS latency 3 for DDR, LPDDR, DDR2
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# and CAS latency 5/CAS write latency 6 for DDR3.
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#
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# Read commands must be sent on phase 0.
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# Write commands must be sent on phase 1.
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#
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from functools import reduce
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from operator import or_
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from migen import *
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from migen.genlib.record import *
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from misoc.interconnect.dfi import *
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from misoc.cores import sdram_settings
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class S6HalfRateDDRPHY(Module):
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def __init__(self, pads, memtype, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
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if memtype not in ["DDR", "LPDDR", "DDR2", "DDR3"]:
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raise NotImplementedError("S6HalfRateDDRPHY only supports DDR, LPDDR, DDR2 and DDR3")
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addressbits = len(pads.a)
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bankbits = len(pads.ba)
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databits = len(pads.dq)
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nphases = 2
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if memtype == "DDR3":
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self.settings = sdram_settings.PhySettings(
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memtype="DDR3",
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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wrphase=1,
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rdcmdphase=1,
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wrcmdphase=0,
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cl=5,
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cwl=6,
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read_latency=6,
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write_latency=2
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)
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else:
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self.settings = sdram_settings.PhySettings(
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memtype=memtype,
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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wrphase=1,
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rdcmdphase=1,
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wrcmdphase=0,
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cl=3,
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read_latency=5,
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write_latency=0
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)
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self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
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self.clk4x_wr_strb = Signal()
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self.clk4x_rd_strb = Signal()
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###
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# sys_clk : system clk, used for dfi interface
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# sdram_half_clk : half rate sdram clk
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# sdram_full_wr_clk : full rate sdram write clk
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# sdram_full_rd_clk : full rate sdram read clk
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sd_sys = getattr(self.sync, "sys")
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sd_sdram_half = getattr(self.sync, "sdram_half")
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sys_clk = ClockSignal("sys")
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sdram_half_clk = ClockSignal("sdram_half")
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sdram_full_wr_clk = ClockSignal("sdram_full_wr")
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sdram_full_rd_clk = ClockSignal("sdram_full_rd")
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#
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# Command/address
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#
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# select active phase
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# sys_clk ----____----____
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# phase_sel(nphases=2) 0 1 0 1 Half Rate
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phase_sel = Signal(log2_int(nphases))
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phase_half = Signal.like(phase_sel)
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phase_sys = Signal.like(phase_half)
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sd_sys += phase_sys.eq(phase_half)
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sd_sdram_half += [
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If(phase_half == phase_sys,
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phase_sel.eq(0),
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).Else(
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phase_sel.eq(phase_sel+1)
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),
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phase_half.eq(phase_half+1),
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]
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# register dfi cmds on half_rate clk
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r_dfi = Array(Record(phase_cmd_description(addressbits, bankbits)) for i in range(nphases))
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for n, phase in enumerate(self.dfi.phases):
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sd_sdram_half += [
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r_dfi[n].reset_n.eq(phase.reset_n),
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r_dfi[n].odt.eq(phase.odt),
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r_dfi[n].address.eq(phase.address),
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r_dfi[n].bank.eq(phase.bank),
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r_dfi[n].cs_n.eq(phase.cs_n),
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r_dfi[n].cke.eq(phase.cke),
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r_dfi[n].cas_n.eq(phase.cas_n),
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r_dfi[n].ras_n.eq(phase.ras_n),
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r_dfi[n].we_n.eq(phase.we_n)
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]
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# output cmds
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sd_sdram_half += [
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pads.a.eq(r_dfi[phase_sel].address),
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pads.ba.eq(r_dfi[phase_sel].bank),
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pads.cke.eq(r_dfi[phase_sel].cke),
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pads.ras_n.eq(r_dfi[phase_sel].ras_n),
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pads.cas_n.eq(r_dfi[phase_sel].cas_n),
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pads.we_n.eq(r_dfi[phase_sel].we_n)
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]
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# optional pads
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for name in "reset_n", "cs_n", "odt":
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if hasattr(pads, name):
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sd_sdram_half += getattr(pads, name).eq(getattr(r_dfi[phase_sel], name))
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#
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# Bitslip
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#
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bitslip_cnt = Signal(4)
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bitslip_inc = Signal()
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sd_sys += [
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If(bitslip_cnt == rd_bitslip,
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bitslip_inc.eq(0)
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).Else(
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bitslip_cnt.eq(bitslip_cnt+1),
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bitslip_inc.eq(1)
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)
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]
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#
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# DQ/DQS/DM data
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#
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sdram_half_clk_n = Signal()
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self.comb += sdram_half_clk_n.eq(~sdram_half_clk)
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postamble = Signal()
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drive_dqs = Signal()
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dqs_t_d0 = Signal()
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dqs_t_d1 = Signal()
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dqs_o = Signal(databits//8)
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dqs_t = Signal(databits//8)
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self.comb += [
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dqs_t_d0.eq(~(drive_dqs | postamble)),
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dqs_t_d1.eq(~drive_dqs),
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]
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for i in range(databits//8):
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# DQS output
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT=dqs_ddr_alignment,
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p_INIT=0,
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p_SRTYPE="ASYNC",
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i_C0=sdram_half_clk,
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i_C1=sdram_half_clk_n,
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i_CE=1,
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i_D0=0,
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i_D1=1,
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i_R=0,
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i_S=0,
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o_Q=dqs_o[i]
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)
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# DQS tristate cmd
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT=dqs_ddr_alignment,
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p_INIT=0,
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p_SRTYPE="ASYNC",
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i_C0=sdram_half_clk,
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i_C1=sdram_half_clk_n,
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i_CE=1,
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i_D0=dqs_t_d0,
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i_D1=dqs_t_d1,
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i_R=0,
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i_S=0,
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o_Q=dqs_t[i]
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)
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# DQS tristate buffer
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if hasattr(pads, "dqs_n"):
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self.specials += Instance("OBUFTDS",
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i_I=dqs_o[i],
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i_T=dqs_t[i],
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o_O=pads.dqs[i],
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o_OB=pads.dqs_n[i],
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)
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else:
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self.specials += Instance("OBUFT",
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i_I=dqs_o[i],
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i_T=dqs_t[i],
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o_O=pads.dqs[i]
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)
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sd_sdram_half += postamble.eq(drive_dqs)
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d_dfi = [Record(phase_wrdata_description(nphases*databits)+phase_rddata_description(nphases*databits))
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for i in range(2*nphases)]
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for n, phase in enumerate(self.dfi.phases):
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self.comb += [
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d_dfi[n].wrdata.eq(phase.wrdata),
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d_dfi[n].wrdata_mask.eq(phase.wrdata_mask),
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d_dfi[n].wrdata_en.eq(phase.wrdata_en),
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d_dfi[n].rddata_en.eq(phase.rddata_en),
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]
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sd_sys += [
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d_dfi[nphases+n].wrdata.eq(phase.wrdata),
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d_dfi[nphases+n].wrdata_mask.eq(phase.wrdata_mask)
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]
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drive_dq = Signal()
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drive_dq_n = [Signal() for i in range(2)]
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self.comb += drive_dq_n[0].eq(~drive_dq)
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sd_sys += drive_dq_n[1].eq(drive_dq_n[0])
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dq_t = Signal(databits)
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dq_o = Signal(databits)
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dq_i = Signal(databits)
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dq_wrdata = []
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for i in range(2):
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for j in reversed(range(nphases)):
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dq_wrdata.append(d_dfi[i*nphases+j].wrdata[:databits])
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dq_wrdata.append(d_dfi[i*nphases+j].wrdata[databits:])
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for i in range(databits):
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# Data serializer
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self.specials += Instance("OSERDES2",
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p_DATA_WIDTH=4,
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p_DATA_RATE_OQ="SDR",
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p_DATA_RATE_OT="SDR",
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p_SERDES_MODE="NONE",
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p_OUTPUT_MODE="SINGLE_ENDED",
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o_OQ=dq_o[i],
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i_OCE=1,
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i_CLK0=sdram_full_wr_clk,
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i_CLK1=0,
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i_IOCE=self.clk4x_wr_strb,
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i_RST=0,
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i_CLKDIV=sys_clk,
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i_D1=dq_wrdata[wr_bitslip+3][i],
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i_D2=dq_wrdata[wr_bitslip+2][i],
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i_D3=dq_wrdata[wr_bitslip+1][i],
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i_D4=dq_wrdata[wr_bitslip+0][i],
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o_TQ=dq_t[i],
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i_T1=drive_dq_n[(wr_bitslip+3)//4],
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i_T2=drive_dq_n[(wr_bitslip+2)//4],
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i_T3=drive_dq_n[(wr_bitslip+1)//4],
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i_T4=drive_dq_n[(wr_bitslip+0)//4],
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i_TRAIN=0,
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i_TCE=1,
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i_SHIFTIN1=0,
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i_SHIFTIN2=0,
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i_SHIFTIN3=0,
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i_SHIFTIN4=0,
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)
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# Data deserializer
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self.specials += Instance("ISERDES2",
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p_DATA_WIDTH=4,
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p_DATA_RATE="SDR",
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p_BITSLIP_ENABLE="TRUE",
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p_SERDES_MODE="NONE",
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p_INTERFACE_TYPE="RETIMED",
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i_D=dq_i[i],
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i_CE0=1,
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i_CLK0=sdram_full_rd_clk,
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i_CLK1=0,
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i_IOCE=self.clk4x_rd_strb,
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i_RST=ResetSignal(),
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i_CLKDIV=sys_clk,
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i_BITSLIP=bitslip_inc,
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o_Q1=d_dfi[0*nphases+0].rddata[i+databits],
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o_Q2=d_dfi[0*nphases+0].rddata[i],
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o_Q3=d_dfi[0*nphases+1].rddata[i+databits],
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o_Q4=d_dfi[0*nphases+1].rddata[i],
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)
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# Data buffer
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self.specials += Instance("IOBUF",
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i_I=dq_o[i],
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o_O=dq_i[i],
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i_T=dq_t[i],
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io_IO=pads.dq[i]
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)
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dq_wrdata_mask = []
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for i in range(2):
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for j in reversed(range(nphases)):
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dq_wrdata_mask.append(d_dfi[i*nphases+j].wrdata_mask[:databits//8])
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dq_wrdata_mask.append(d_dfi[i*nphases+j].wrdata_mask[databits//8:])
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for i in range(databits//8):
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# Mask serializer
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self.specials += Instance("OSERDES2",
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p_DATA_WIDTH=4,
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p_DATA_RATE_OQ="SDR",
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p_DATA_RATE_OT="SDR",
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p_SERDES_MODE="NONE",
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p_OUTPUT_MODE="SINGLE_ENDED",
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o_OQ=pads.dm[i],
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i_OCE=1,
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i_CLK0=sdram_full_wr_clk,
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i_CLK1=0,
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i_IOCE=self.clk4x_wr_strb,
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i_RST=0,
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i_CLKDIV=sys_clk,
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i_D1=dq_wrdata_mask[wr_bitslip+3][i],
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i_D2=dq_wrdata_mask[wr_bitslip+2][i],
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i_D3=dq_wrdata_mask[wr_bitslip+1][i],
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i_D4=dq_wrdata_mask[wr_bitslip+0][i],
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i_TRAIN=0,
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i_TCE=0,
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i_SHIFTIN1=0,
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i_SHIFTIN2=0,
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i_SHIFTIN3=0,
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i_SHIFTIN4=0,
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)
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#
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# DQ/DQS/DM control
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#
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# write
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wrdata_en = Signal()
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self.comb += wrdata_en.eq(reduce(or_, [d_dfi[p].wrdata_en for p in range(nphases)]))
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if memtype == "DDR3":
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r_drive_dq = Signal(self.settings.cwl-1)
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sd_sdram_half += r_drive_dq.eq(Cat(wrdata_en, r_drive_dq))
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self.comb += drive_dq.eq(r_drive_dq[self.settings.cwl-2])
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else:
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self.comb += drive_dq.eq(wrdata_en)
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wrdata_en_d = Signal()
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sd_sys += wrdata_en_d.eq(wrdata_en)
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r_dfi_wrdata_en = Signal(max(self.settings.cwl, self.settings.cl))
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sd_sdram_half += r_dfi_wrdata_en.eq(Cat(wrdata_en_d, r_dfi_wrdata_en))
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if memtype == "DDR3":
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self.comb += drive_dqs.eq(r_dfi_wrdata_en[self.settings.cwl-1])
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else:
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self.comb += drive_dqs.eq(r_dfi_wrdata_en[1])
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# read
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rddata_en = Signal()
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self.comb += rddata_en.eq(reduce(or_, [d_dfi[p].rddata_en for p in range(nphases)]))
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rddata_sr = Signal(self.settings.read_latency)
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sd_sys += rddata_sr.eq(Cat(rddata_sr[1:self.settings.read_latency], rddata_en))
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for n, phase in enumerate(self.dfi.phases):
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self.comb += [
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phase.rddata.eq(d_dfi[n].rddata),
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phase.rddata_valid.eq(rddata_sr[0]),
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]
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class S6QuarterRateDDRPHY(Module):
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def __init__(self, pads, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
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half_rate_phy = S6HalfRateDDRPHY(pads, "DDR3", rd_bitslip, wr_bitslip, dqs_ddr_alignment)
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self.submodules += RenameClockDomains(half_rate_phy, {"sys" : "sys2x"})
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addressbits = len(pads.a)
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bankbits = len(pads.ba)
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databits = len(pads.dq)
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nphases = 4
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self.settings = sdram_settings.PhySettings(
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memtype="DDR3",
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dfi_databits=2*databits,
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nphases=nphases,
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rdphase=0,
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wrphase=1,
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rdcmdphase=1,
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wrcmdphase=0,
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cl=5,
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cwl=6,
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read_latency=6//2+1,
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write_latency=2//2
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)
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self.dfi = Interface(addressbits, bankbits, 2*databits, nphases)
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self.clk8x_wr_strb = half_rate_phy.clk4x_wr_strb
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self.clk8x_rd_strb = half_rate_phy.clk4x_rd_strb
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# sys_clk : system clk, used for dfi interface
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# sys2x_clk : 2x system clk
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sd_sys = getattr(self.sync, "sys")
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sd_sys2x = getattr(self.sync, "sys2x")
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# select active sys2x phase
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# sys_clk ----____----____
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# phase_sel 0 1 0 1
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phase_sel = Signal()
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phase_sys2x = Signal.like(phase_sel)
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phase_sys = Signal.like(phase_sys2x)
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sd_sys += phase_sys.eq(phase_sys2x)
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sd_sys2x += [
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If(phase_sys2x == phase_sys,
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phase_sel.eq(0),
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).Else(
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phase_sel.eq(~phase_sel)
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),
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phase_sys2x.eq(~phase_sel)
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]
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# DFI adaptation
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# Commands and writes
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dfi_leave_out = set(["rddata", "rddata_valid", "wrdata_en"])
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self.comb += [
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If(~phase_sel,
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Record.connect(self.dfi.phases[0], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
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Record.connect(self.dfi.phases[1], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
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).Else(
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Record.connect(self.dfi.phases[2], half_rate_phy.dfi.phases[0], leave_out=dfi_leave_out),
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Record.connect(self.dfi.phases[3], half_rate_phy.dfi.phases[1], leave_out=dfi_leave_out),
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),
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]
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wr_data_en = self.dfi.phases[self.settings.wrphase].wrdata_en & ~phase_sel
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wr_data_en_d = Signal()
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sd_sys2x += wr_data_en_d.eq(wr_data_en)
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self.comb += half_rate_phy.dfi.phases[half_rate_phy.settings.wrphase].wrdata_en.eq(wr_data_en | wr_data_en_d)
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|
|
|
# Reads
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rddata = Array(Signal(2*databits) for i in range(2))
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|
rddata_valid = Signal(2)
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|
|
|
for i in range(2):
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|
sd_sys2x += [
|
|
rddata_valid[i].eq(half_rate_phy.dfi.phases[i].rddata_valid),
|
|
rddata[i].eq(half_rate_phy.dfi.phases[i].rddata)
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|
]
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|
|
|
sd_sys += [
|
|
self.dfi.phases[0].rddata.eq(rddata[0]),
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|
self.dfi.phases[0].rddata_valid.eq(rddata_valid[0]),
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|
self.dfi.phases[1].rddata.eq(rddata[1]),
|
|
self.dfi.phases[1].rddata_valid.eq(rddata_valid[1]),
|
|
self.dfi.phases[2].rddata.eq(half_rate_phy.dfi.phases[0].rddata),
|
|
self.dfi.phases[2].rddata_valid.eq(half_rate_phy.dfi.phases[0].rddata_valid),
|
|
self.dfi.phases[3].rddata.eq(half_rate_phy.dfi.phases[1].rddata),
|
|
self.dfi.phases[3].rddata_valid.eq(half_rate_phy.dfi.phases[1].rddata_valid)
|
|
]
|