148 lines
5.2 KiB
Python
148 lines
5.2 KiB
Python
from migen import *
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from migen.util.misc import xdir
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from migen.fhdl.tracer import get_obj_var_name
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class _CSRBase(DUID):
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def __init__(self, size, name):
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DUID.__init__(self)
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self.name = get_obj_var_name(name)
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if self.name is None:
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raise ValueError("Cannot extract CSR name from code, need to specify.")
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self.size = size
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class CSR(_CSRBase):
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def __init__(self, size=1, name=None):
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_CSRBase.__init__(self, size, name)
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self.re = Signal(name=self.name + "_re")
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self.r = Signal(self.size, name=self.name + "_r")
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self.w = Signal(self.size, name=self.name + "_w")
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class _CompoundCSR(_CSRBase, Module):
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def __init__(self, size, name):
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_CSRBase.__init__(self, size, name)
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self.simple_csrs = []
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def get_simple_csrs(self):
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if not self.finalized:
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raise FinalizeError
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return self.simple_csrs
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def do_finalize(self, busword):
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raise NotImplementedError
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class CSRStatus(_CompoundCSR):
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def __init__(self, size=1, reset=0, name=None):
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_CompoundCSR.__init__(self, size, name)
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self.status = Signal(self.size, reset=reset)
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def do_finalize(self, busword):
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nwords = (self.size + busword - 1)//busword
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for i in reversed(range(nwords)):
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nbits = min(self.size - i*busword, busword)
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sc = CSR(nbits, self.name + str(i) if nwords > 1 else self.name)
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self.comb += sc.w.eq(self.status[i*busword:i*busword+nbits])
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self.simple_csrs.append(sc)
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class CSRStorage(_CompoundCSR):
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def __init__(self, size=1, reset=0, atomic_write=False, write_from_dev=False, alignment_bits=0, name=None):
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_CompoundCSR.__init__(self, size, name)
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self.alignment_bits = alignment_bits
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self.storage_full = Signal(self.size, reset=reset)
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self.storage = Signal(self.size - self.alignment_bits, reset=reset >> alignment_bits)
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self.comb += self.storage.eq(self.storage_full[self.alignment_bits:])
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self.atomic_write = atomic_write
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self.re = Signal()
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if write_from_dev:
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self.we = Signal()
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self.dat_w = Signal(self.size - self.alignment_bits)
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self.sync += If(self.we, self.storage_full.eq(self.dat_w << self.alignment_bits))
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def do_finalize(self, busword):
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nwords = (self.size + busword - 1)//busword
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if nwords > 1 and self.atomic_write:
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backstore = Signal(self.size - busword, name=self.name + "_backstore")
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for i in reversed(range(nwords)):
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nbits = min(self.size - i*busword, busword)
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sc = CSR(nbits, self.name + str(i) if nwords else self.name)
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self.simple_csrs.append(sc)
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lo = i*busword
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hi = lo+nbits
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# read
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if lo >= self.alignment_bits:
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self.comb += sc.w.eq(self.storage_full[lo:hi])
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elif hi > self.alignment_bits:
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self.comb += sc.w.eq(Cat(Replicate(0, hi - self.alignment_bits),
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self.storage_full[self.alignment_bits:hi]))
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else:
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self.comb += sc.w.eq(0)
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# write
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if nwords > 1 and self.atomic_write:
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if i:
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self.sync += If(sc.re, backstore[lo-busword:hi-busword].eq(sc.r))
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else:
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self.sync += If(sc.re, self.storage_full.eq(Cat(sc.r, backstore)))
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else:
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self.sync += If(sc.re, self.storage_full[lo:hi].eq(sc.r))
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self.sync += self.re.eq(sc.re)
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def csrprefix(prefix, csrs, done):
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for csr in csrs:
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if csr.duid not in done:
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csr.name = prefix + csr.name
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done.add(csr.duid)
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def memprefix(prefix, memories, done):
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for memory in memories:
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if memory.duid not in done:
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memory.name_override = prefix + memory.name_override
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done.add(memory.duid)
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def _make_gatherer(method, cls, prefix_cb):
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def gatherer(self):
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try:
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exclude = self.autocsr_exclude
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except AttributeError:
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exclude = {}
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try:
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prefixed = self.__prefixed
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except AttributeError:
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prefixed = self.__prefixed = set()
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r = []
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for k, v in xdir(self, True):
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if k not in exclude:
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if isinstance(v, cls):
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r.append(v)
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elif hasattr(v, method) and callable(getattr(v, method)):
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items = getattr(v, method)()
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prefix_cb(k + "_", items, prefixed)
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r += items
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return sorted(r, key=lambda x: x.duid)
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return gatherer
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class AutoCSR:
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get_memories = _make_gatherer("get_memories", Memory, memprefix)
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get_csrs = _make_gatherer("get_csrs", _CSRBase, csrprefix)
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class GenericBank(Module):
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def __init__(self, description, busword):
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# Turn description into simple CSRs and claim ownership of compound CSR modules
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self.simple_csrs = []
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for c in description:
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if isinstance(c, CSR):
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self.simple_csrs.append(c)
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else:
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c.finalize(busword)
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self.simple_csrs += c.get_simple_csrs()
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self.submodules += c
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self.decode_bits = bits_for(len(self.simple_csrs)-1)
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