80 lines
2.8 KiB
Python
80 lines
2.8 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fsm import FSM, NextState
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from migen.actorlib.fifo import SyncFIFO as FIFO
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from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.frontend.dma.common import *
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class DMAReader(Module, AutoCSR):
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def __init__(self, endpoint, port, table_depth=256):
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self.source = Source(dma_layout(endpoint.phy.dw))
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self._enable = CSRStorage()
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# # #
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enable = self._enable.storage
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max_words_per_request = max_request_size//(endpoint.phy.dw//8)
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max_pending_words = endpoint.max_pending_requests*max_words_per_request
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fifo_depth = 2*max_pending_words
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# Request generation
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# requests from table are splitted in chunks of "max_size"
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self.table = table = DMARequestTable(table_depth)
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splitter = InsertReset(DMARequestSplitter(endpoint.phy.max_request_size))
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self.submodules += table, splitter
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self.comb += splitter.reset.eq(~enable)
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self.comb += table.source.connect(splitter.sink)
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# Request FSM
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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request_ready = Signal()
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fsm.act("IDLE",
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If(request_ready,
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NextState("REQUEST"),
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)
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)
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fsm.act("REQUEST",
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port.source.stb.eq(1),
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port.source.channel.eq(port.channel),
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port.source.user_id.eq(splitter.source.user_id),
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port.source.sop.eq(1),
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port.source.eop.eq(1),
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port.source.we.eq(0),
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port.source.adr.eq(splitter.source.address),
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port.source.len.eq(splitter.source.length[2:]),
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port.source.req_id.eq(endpoint.phy.id),
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port.source.dat.eq(0),
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If(port.source.ack,
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splitter.source.ack.eq(1),
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NextState("IDLE"),
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)
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)
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# Data FIFO
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# issue read requests when enough space available in fifo
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fifo = InsertReset(FIFO(dma_layout(endpoint.phy.dw), fifo_depth, buffered=True))
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self.submodules += fifo
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self.comb += fifo.reset.eq(~enable)
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last_user_id = Signal(8, reset=255)
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self.sync += \
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If(port.sink.stb & port.sink.sop & port.sink.ack,
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last_user_id.eq(port.sink.user_id)
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)
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self.comb += [
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fifo.sink.stb.eq(port.sink.stb),
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fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)),
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fifo.sink.dat.eq(port.sink.dat),
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port.sink.ack.eq(fifo.sink.ack | ~enable),
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]
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self.comb += Record.connect(fifo.source, self.source)
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fifo_ready = fifo.fifo.level < (fifo_depth//2)
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self.comb += request_ready.eq(splitter.source.stb & fifo_ready)
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