89 lines
2.9 KiB
Python
89 lines
2.9 KiB
Python
from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.genlib.fifo import SyncFIFOBuffered as SyncFIFO
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from migen.genlib.fsm import FSM, NextState
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from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.frontend.dma.common import *
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class DMAWriter(Module, AutoCSR):
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def __init__(self, endpoint, port, table_depth=256):
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self.sink = sink = Sink(dma_layout(endpoint.phy.dw))
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self._enable = CSRStorage()
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# # #
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enable = self._enable.storage
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max_words_per_request = max_request_size//(endpoint.phy.dw//8)
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fifo_depth = 4*max_words_per_request
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# Data FIFO
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# store data until we have enough data to issue a
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# write request
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fifo = InsertReset(SyncFIFO(endpoint.phy.dw, fifo_depth))
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self.submodules += fifo
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self.comb += [
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fifo.we.eq(sink.stb & enable),
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sink.ack.eq(fifo.writable & sink.stb & enable),
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fifo.din.eq(sink.dat),
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fifo.reset.eq(~enable)
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]
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# Request generation
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# requests from table are splitted in chunks of "max_size"
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self.table = table = DMARequestTable(table_depth)
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splitter = InsertReset(DMARequestSplitter(endpoint.phy.max_payload_size))
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self.submodules += table, splitter
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self.comb += splitter.reset.eq(~enable)
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self.comb += table.source.connect(splitter.sink)
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# Request FSM
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cnt = Signal(max=(2**flen(endpoint.phy.max_payload_size))/8)
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clr_cnt = Signal()
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inc_cnt = Signal()
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self.sync += \
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If(clr_cnt,
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cnt.eq(0)
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).Elif(inc_cnt,
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cnt.eq(cnt + 1)
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)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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request_ready = Signal()
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fsm.act("IDLE",
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clr_cnt.eq(1),
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If(request_ready,
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NextState("REQUEST"),
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)
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)
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fsm.act("REQUEST",
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inc_cnt.eq(port.source.stb & port.source.ack),
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port.source.stb.eq(1),
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port.source.channel.eq(port.channel),
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port.source.user_id.eq(splitter.source.user_id),
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port.source.sop.eq(cnt == 0),
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port.source.eop.eq(cnt == splitter.source.length[3:]-1),
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port.source.we.eq(1),
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port.source.adr.eq(splitter.source.address),
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port.source.req_id.eq(endpoint.phy.id),
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port.source.tag.eq(0),
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port.source.len.eq(splitter.source.length[2:]),
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port.source.dat.eq(fifo.dout),
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If(port.source.ack,
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fifo.re.eq(1),
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If(port.source.eop,
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splitter.source.ack.eq(1),
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NextState("IDLE"),
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)
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)
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)
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fifo_ready = fifo.level >= splitter.source.length[3:]
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self.sync += request_ready.eq(splitter.source.stb & fifo_ready)
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