320 lines
9.0 KiB
Python
320 lines
9.0 KiB
Python
import math
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from migen.fhdl.std import *
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from migen.flow.actor import *
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from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
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from migen.fhdl.specials import *
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from migen.genlib.cdc import MultiReg
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from misoclib.com.liteusb.common import *
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def anti_starvation(module, timeout):
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en = Signal()
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max_time = Signal()
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if timeout:
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t = timeout - 1
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time = Signal(max=t+1)
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module.comb += max_time.eq(time == 0)
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module.sync += If(~en,
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time.eq(t)
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).Elif(~max_time,
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time.eq(time - 1)
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)
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else:
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module.comb += max_time.eq(0)
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return en, max_time
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class FT245PHYSynchronous(Module):
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def __init__(self, pads, clk_freq,
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fifo_depth=32,
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read_time=128,
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write_time=128):
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dw = flen(pads.data)
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# read fifo (FTDI --> SoC)
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read_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
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{"write": "usb", "read": "sys"})
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read_buffer = RenameClockDomains(SyncFIFO(phy_description(8), 4),
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{"sys": "usb"})
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self.comb += read_buffer.source.connect(read_fifo.sink)
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# write fifo (SoC --> FTDI)
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write_fifo = RenameClockDomains(AsyncFIFO(phy_description(8), fifo_depth),
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{"write": "sys", "read": "usb"})
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self.submodules += read_fifo, read_buffer, write_fifo
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# sink / source interfaces
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self.sink = write_fifo.sink
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self.source = read_fifo.source
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# read / write arbitration
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wants_write = Signal()
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wants_read = Signal()
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txe_n = Signal()
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rxf_n = Signal()
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self.comb += [
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txe_n.eq(pads.txe_n),
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rxf_n.eq(pads.rxf_n),
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wants_write.eq(~txe_n & write_fifo.source.stb),
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wants_read.eq(~rxf_n & read_fifo.sink.ack),
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]
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read_time_en, max_read_time = anti_starvation(self, read_time)
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write_time_en, max_write_time = anti_starvation(self, write_time)
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data_w_accepted = Signal(reset=1)
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fsm = FSM(reset_state="READ")
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self.submodules += RenameClockDomains(fsm, {"sys": "usb"})
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fsm.act("READ",
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read_time_en.eq(1),
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If(wants_write,
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If(~wants_read | max_read_time,
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NextState("RTW")
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)
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)
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)
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fsm.act("RTW",
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NextState("WRITE")
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)
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fsm.act("WRITE",
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write_time_en.eq(1),
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If(wants_read,
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If(~wants_write | max_write_time,
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NextState("WTR")
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)
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),
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write_fifo.source.ack.eq(wants_write & data_w_accepted)
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)
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fsm.act("WTR",
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NextState("READ")
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)
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# databus tristate
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data_w = Signal(dw)
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data_r = Signal(dw)
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data_oe = Signal()
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self.specials += Tristate(pads.data, data_w, data_oe, data_r)
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# read / write actions
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pads.oe_n.reset = 1
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pads.rd_n.reset = 1
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pads.wr_n.reset = 1
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self.sync.usb += [
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If(fsm.ongoing("READ"),
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data_oe.eq(0),
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pads.oe_n.eq(0),
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pads.rd_n.eq(~wants_read),
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pads.wr_n.eq(1)
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).Elif(fsm.ongoing("WRITE"),
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data_oe.eq(1),
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pads.oe_n.eq(1),
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pads.rd_n.eq(1),
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pads.wr_n.eq(~wants_write),
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data_w_accepted.eq(~txe_n)
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).Else(
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data_oe.eq(1),
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pads.oe_n.eq(~fsm.ongoing("WTR")),
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pads.rd_n.eq(1),
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pads.wr_n.eq(1)
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),
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read_buffer.sink.stb.eq(~pads.rd_n & ~rxf_n),
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read_buffer.sink.data.eq(data_r),
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If(~txe_n & data_w_accepted,
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data_w.eq(write_fifo.source.data)
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)
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]
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class FT245PHYAsynchronous(Module):
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def __init__(self, pads, clk_freq,
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fifo_depth=32,
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read_time=128,
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write_time=128):
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dw = flen(pads.data)
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self.clk_freq = clk_freq
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# timings
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tRD = self.ns(30) # RD# active pulse width (t4)
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tRDDataSetup = self.ns(14) # RD# to DATA (t3)
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tWRDataSetup = self.ns(5) # DATA to WR# active setup time (t8)
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tWR = self.ns(30) # WR# active pulse width (t10)
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tMultiReg = 2
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# read fifo (FTDI --> SoC)
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read_fifo = SyncFIFO(phy_description(8), fifo_depth)
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# write fifo (SoC --> FTDI)
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write_fifo = SyncFIFO(phy_description(8), fifo_depth)
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self.submodules += read_fifo, write_fifo
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# sink / source interfaces
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self.sink = write_fifo.sink
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self.source = read_fifo.source
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# read / write arbitration
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wants_write = Signal()
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wants_read = Signal()
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txe_n = Signal()
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rxf_n = Signal()
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self.specials += [
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MultiReg(pads.txe_n, txe_n),
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MultiReg(pads.rxf_n, rxf_n)
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]
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self.comb += [
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wants_write.eq(~txe_n & write_fifo.source.stb),
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wants_read.eq(~rxf_n & read_fifo.sink.ack),
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]
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read_time_en, max_read_time = anti_starvation(self, read_time)
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write_time_en, max_write_time = anti_starvation(self, write_time)
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fsm = FSM(reset_state="READ")
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self.submodules += fsm
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read_done = Signal()
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write_done = Signal()
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commuting = Signal()
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fsm.act("READ",
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read_time_en.eq(1),
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If(wants_write & read_done,
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If(~wants_read | max_read_time,
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commuting.eq(1),
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NextState("RTW")
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)
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)
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)
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fsm.act("RTW",
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NextState("WRITE")
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)
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fsm.act("WRITE",
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write_time_en.eq(1),
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If(wants_read & write_done,
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If(~wants_write | max_write_time,
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commuting.eq(1),
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NextState("WTR")
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)
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)
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)
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fsm.act("WTR",
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NextState("READ")
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)
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# databus tristate
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data_w = Signal(dw)
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data_r_async = Signal(dw)
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data_r = Signal(dw)
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data_oe = Signal()
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self.specials += [
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Tristate(pads.data, data_w, data_oe, data_r_async),
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MultiReg(data_r_async, data_r)
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]
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# read actions
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pads.rd_n.reset = 1
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read_fsm = FSM(reset_state="IDLE")
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read_counter = Counter(8)
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self.submodules += read_fsm, read_counter
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read_fsm.act("IDLE",
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read_done.eq(1),
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read_counter.reset.eq(1),
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If(fsm.ongoing("READ") & wants_read,
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If(~commuting,
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NextState("PULSE_RD_N")
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)
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)
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)
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read_fsm.act("PULSE_RD_N",
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pads.rd_n.eq(0),
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read_counter.ce.eq(1),
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If(read_counter.value == max((tRD-1), (tRDDataSetup + tMultiReg -1)),
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NextState("ACQUIRE_DATA")
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)
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)
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read_fsm.act("ACQUIRE_DATA",
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read_fifo.sink.stb.eq(1),
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read_fifo.sink.data.eq(data_r),
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NextState("WAIT_RXF_N")
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)
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read_fsm.act("WAIT_RXF_N",
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If(rxf_n,
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NextState("IDLE")
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)
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)
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# write actions
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pads.wr_n.reset = 1
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write_fsm = FSM(reset_state="IDLE")
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write_counter = Counter(8)
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self.submodules += write_fsm, write_counter
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write_fsm.act("IDLE",
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write_done.eq(1),
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write_counter.reset.eq(1),
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If(fsm.ongoing("WRITE") & wants_write,
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If(~commuting,
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NextState("SET_DATA")
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)
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)
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)
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write_fsm.act("SET_DATA",
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data_oe.eq(1),
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data_w.eq(write_fifo.source.data),
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write_counter.ce.eq(1),
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If(write_counter.value == (tWRDataSetup-1),
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write_counter.reset.eq(1),
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NextState("PULSE_WR_N")
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)
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)
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write_fsm.act("PULSE_WR_N",
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data_oe.eq(1),
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data_w.eq(write_fifo.source.data),
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pads.wr_n.eq(0),
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write_counter.ce.eq(1),
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If(write_counter.value == (tWR-1),
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NextState("WAIT_TXE_N")
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)
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)
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write_fsm.act("WAIT_TXE_N",
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If(txe_n,
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write_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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def ns(self, t, margin=True):
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clk_period_ns = 1000000000/self.clk_freq
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if margin:
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t += clk_period_ns/2
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return math.ceil(t/clk_period_ns)
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def FT245PHY(pads, *args, **kwargs):
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# autodetect PHY
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if hasattr(pads, "oe_n"):
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return FT245PHYSynchronous(pads, *args, **kwargs)
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else:
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return FT245PHYAsynchronous(pads, *args, **kwargs)
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