Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.		2012-02-18 18:12:14 +01:00
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dfii	Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately.	2012-02-18 18:12:14 +01:00
lm32	lm32: compatibility with the new instance API	2012-02-16 18:35:22 +01:00
m1crg	Connect DDR PHY	2012-02-17 11:04:44 +01:00
norflash	Use new bus API	2012-02-15 16:55:13 +01:00
s6ddrphy	Map DDR PHY controls in CSR	2012-02-17 17:34:59 +01:00
sram	Use new bus API	2012-02-15 16:55:13 +01:00
uart	uart: RX support	2012-02-07 14:12:23 +01:00
__init__.py	Initial import	2011-12-13 17:33:12 +01:00