74 lines
2.4 KiB
Python
74 lines
2.4 KiB
Python
from migen import *
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from migen.genlib.record import *
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def phase_cmd_description(addressbits, bankbits):
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return [
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("address", addressbits, DIR_M_TO_S),
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("bank", bankbits, DIR_M_TO_S),
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("cas_n", 1, DIR_M_TO_S),
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("cs_n", 1, DIR_M_TO_S),
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("ras_n", 1, DIR_M_TO_S),
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("we_n", 1, DIR_M_TO_S),
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("cke", 1, DIR_M_TO_S),
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("odt", 1, DIR_M_TO_S),
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("reset_n", 1, DIR_M_TO_S)
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]
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def phase_wrdata_description(databits):
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return [
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("wrdata", databits, DIR_M_TO_S),
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("wrdata_en", 1, DIR_M_TO_S),
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("wrdata_mask", databits//8, DIR_M_TO_S)
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]
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def phase_rddata_description(databits):
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return [
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("rddata_en", 1, DIR_M_TO_S),
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("rddata", databits, DIR_S_TO_M),
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("rddata_valid", 1, DIR_S_TO_M)
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]
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def phase_description(addressbits, bankbits, databits):
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r = phase_cmd_description(addressbits, bankbits)
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r += phase_wrdata_description(databits)
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r += phase_rddata_description(databits)
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return r
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class Interface(Record):
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def __init__(self, addressbits, bankbits, databits, nphases=1):
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layout = [("p"+str(i), phase_description(addressbits, bankbits, databits)) for i in range(nphases)]
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Record.__init__(self, layout)
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self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
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for p in self.phases:
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p.cas_n.reset = 1
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p.cs_n.reset = 1
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p.ras_n.reset = 1
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p.we_n.reset = 1
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# Returns pairs (DFI-mandated signal name, Migen signal object)
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def get_standard_names(self, m2s=True, s2m=True):
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r = []
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add_suffix = len(self.phases) > 1
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for n, phase in enumerate(self.phases):
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for field, size, direction in phase.layout:
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if (m2s and direction == DIR_M_TO_S) or (s2m and direction == DIR_S_TO_M):
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if add_suffix:
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if direction == DIR_M_TO_S:
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suffix = "_p" + str(n)
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else:
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suffix = "_w" + str(n)
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else:
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suffix = ""
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r.append(("dfi_" + field + suffix, getattr(phase, field)))
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return r
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class Interconnect(Module):
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def __init__(self, master, slave):
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self.comb += master.connect(slave)
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