18 lines
490 B
Python
18 lines
490 B
Python
from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.genlib.io import CRG
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from misoclib.soc import SoC
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class BaseSoC(SoC):
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default_platform = "versa"
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def __init__(self, platform, **kwargs):
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SoC.__init__(self, platform,
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clk_freq=100*1000000,
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integrated_rom_size=0x8000,
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**kwargs)
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self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
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self.comb += platform.request("user_led", 0).eq(ResetSignal())
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default_subtarget = BaseSoC
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