100 lines
3.6 KiB
Python
100 lines
3.6 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.bank.description import *
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from migen.bank.eventmanager import *
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from migen.bank import csrgen
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from migen.bus import wishbone
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_count_width = 11
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class MiniMAC:
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def __init__(self, address):
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# PHY signals
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self.phy_tx_clk = Signal()
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self.phy_tx_data = Signal(4)
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self.phy_tx_en = Signal()
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self.phy_tx_er = Signal()
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self.phy_rx_clk = Signal()
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self.phy_rx_data = Signal(4)
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self.phy_dv = Signal()
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self.phy_rx_er = Signal()
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self.phy_col = Signal()
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self.phy_crs = Signal()
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self.phy_rst_n = Signal()
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# CPU interface
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self._phy_reset = RegisterField("phy_reset", reset=1)
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self._rx_count_0 = RegisterField("rx_count_0", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._rx_count_1 = RegisterField("rx_count_1", _count_width, access_bus=READ_ONLY, access_dev=WRITE_ONLY)
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self._tx_count = RegisterField("tx_count", _count_width, access_dev=READ_WRITE)
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self._tx_start = RegisterRaw("tx_start")
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regs = [self._phy_reset, self._rx_count_0, self._rx_count_1, self._tx_count, self._tx_start]
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self._rx_event_0 = EventSourcePulse()
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self._rx_event_1 = EventSourcePulse()
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self._tx_event = EventSourcePulse()
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self.events = EventManager(self._rx_event_0, self._rx_event_1, self._tx_event)
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self.bank = csrgen.Bank(regs + self.events.get_registers(), address=address)
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self.membus = wishbone.Interface()
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def get_fragment(self):
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init = Signal(reset=1)
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rx_ready_0 = Signal()
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rx_ready_1 = Signal()
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rx_pending_0 = self._rx_event_0.pending
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rx_pending_1 = self._rx_event_1.pending
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rx_pending_0_r = Signal()
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rx_pending_1_r = Signal()
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comb = [
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self.phy_rst_n.eq(~self._phy_reset.field.r),
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rx_ready_0.eq(init | (rx_pending_0_r & ~rx_pending_0)),
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rx_ready_1.eq(init | (rx_pending_1_r & ~rx_pending_1)),
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self._tx_count.field.w.eq(0),
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self._tx_count.field.we.eq(self._tx_event.trigger)
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]
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sync = [
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init.eq(0),
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rx_pending_0_r.eq(rx_pending_0),
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rx_pending_1_r.eq(rx_pending_1)
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]
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inst = Instance("minimac3",
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Instance.ClockPort("sys_clk"),
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Instance.ResetPort("sys_rst"),
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Instance.Output("rx_done_0", self._rx_event_0.trigger),
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Instance.Output("rx_count_0", self._rx_count_0.field.w),
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Instance.Output("rx_done_1", self._rx_event_1.trigger),
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Instance.Output("rx_count_1", self._rx_count_1.field.w),
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Instance.Input("rx_ready_0", rx_ready_0),
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Instance.Input("rx_ready_1", rx_ready_1),
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Instance.Input("tx_start", self._tx_start.re),
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Instance.Input("tx_count", self._tx_count.field.r),
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Instance.Output("tx_done", self._tx_event.trigger),
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Instance.Input("wb_adr_i", self.membus.adr),
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Instance.Input("wb_dat_i", self.membus.dat_w),
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Instance.Input("wb_sel_i", self.membus.sel),
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Instance.Input("wb_stb_i", self.membus.stb),
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Instance.Input("wb_cyc_i", self.membus.cyc),
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Instance.Input("wb_we_i", self.membus.we),
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Instance.Output("wb_dat_o", self.membus.dat_r),
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Instance.Output("wb_ack_o", self.membus.ack),
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Instance.ClockPort("phy_tx_clk", "eth_tx"),
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Instance.Output("phy_tx_data", self.phy_tx_data),
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Instance.Output("phy_tx_en", self.phy_tx_en),
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Instance.Output("phy_tx_er", self.phy_tx_er),
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Instance.ClockPort("phy_rx_clk", "eth_rx"),
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Instance.Input("phy_rx_data", self.phy_rx_data),
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Instance.Input("phy_dv", self.phy_dv),
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Instance.Input("phy_rx_er", self.phy_rx_er),
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Instance.Input("phy_col", self.phy_col),
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Instance.Input("phy_crs", self.phy_crs))
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return Fragment(comb, sync, specials={inst}) \
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+ self.events.get_fragment() \
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+ self.bank.get_fragment()
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