228 lines
6.1 KiB
Python
228 lines
6.1 KiB
Python
from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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class LiteEthEtherboneDepacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_udp_user_description(8),
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eth_etherbone_description(8),
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etherbone_header,
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etherbone_header_len)
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class LiteEthEtherbonePacketizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_etherbone_description(8),
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eth_udp_user_description(8),
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etherbone_header,
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etherbone_header_len)
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class LiteEthEtherboneTX(Module):
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def __init__(self, udp_port):
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self.sink = sink = Sink(eth_etherbone_user_description(8))
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self.source = source = Source(eth_udp_user_description(8))
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###
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self.submodules.packetizer = packetizer = LiteEthUDPPacketizer()
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self.comb += [
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packetizer.sink.stb.eq(sink.stb),
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packetizer.sink.sop.eq(sink.sop),
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packetizer.sink.eop.eq(sink.eop),
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sink.ack.eq(packetizer.sink.ack),
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packetizer.sink.magic.eq(etherbone_magic),
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packetizer.sink.portsize.eq(32), # XXX
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packetizer.sink.addrsize.eq(32), # XXX
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packetizer.sink.pf.eq(0), # XXX
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packetizer.sink.version.eq(etherbone_version),
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packetizer.sink.wff.eq(0), # XXX
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packetizer.sink.wca.eq(0), # XXX
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packetizer.sink.cyc.eq(0), # XXX
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packetizer.sink.rff.eq(0), # XXX
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packetizer.sink.rca.eq(0), # XXX
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packetizer.sink.bca.eq(0), # XXX
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packetizer.sink.rcount.eq(sink.rcount),
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packetier.sink.wconut.eq(sink.wcount),
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packetizer.sink.data.eq(sink.data)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.sop,
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packetizer.source.ack.eq(0),
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NextState("SEND")
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)
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)
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self.comb += [
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source.src_port.eq(0x1234), # XXX,
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source.dst_port.eq(udp_port),
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source.ip_address.eq(sink.ip_address),
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source.length.eq(sink.length + eth_etherbone_header_len)
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]
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fsm.act("SEND",
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Record.connect(packetizer.source, source),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthEtherboneRX(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_udp_user_description(8))
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self.source = source = Source(eth_etherbone_user_description(8))
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###
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self.submodules.depacketizer = depacketizer = LiteEtherboneDepacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.sync += valid.eq(
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depacketizer.source.stb &
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(depacketizer.source.magic == etherbone_magic) &
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(depacketizer.source.version == etherbone_version)
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)
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fsm.act("CHECK",
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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)
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)
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self.comb += [
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source.sop.eq(depacketizer.source.sop),
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source.eop.eq(depacketizer.source.eop),
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source.rcount.eq(depacketizer.source.rcount),
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source.wcount.eq(depacketizer.source.wcount),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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]
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fsm.act("PRESENT",
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source.stb.eq(depacketizer.source.stb),
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depacketizer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthEtherboneWishboneMaster(Module):
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def __init__(self):
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self.sink = sink = Sink(eth_etherbone_user_description(8))
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self.source = source = Source(eth_etherbone_description(8))
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self.bus = bus = wishbone.Interface()
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###
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self.submodules.base_addr = base_addr = FlipFlop(32)
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self.comb += self.base_addr.d.eq(self.sink.data)
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self.submodules.counter = counter = Counter(32)
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self.submodules.fifo = fifo = SyncFIFO([("data", 32)], 256)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter.reset.eq(1),
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If(sink.stb & sink.sop,
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If(sink.wcount > 0,
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self.base_addr.ce.eq(1),
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NextState("WRITE_DATA")
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).Elif(sink.rcount > 0,
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self.base_addr.ce.eq(1),
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NextState("READ_DATA")
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)
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)
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)
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fsm.act("WRITE_DATA",
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bus.adr.eq(base_addr + self.counter.value),
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bus.dat_w.eq(sink.data),
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bus.sel.eq(0xf), # XXX?
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bus.stb.eq(sink.stb),
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bus.we.eq(1),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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sink.ack.eq(1),
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counter.ce.eq(1),
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If(counter.value == sink.wcount-1,
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If(sink.rcount > 0,
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counter.reset.eq(1)
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NextState("READ_DATA")
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).Else(
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NextState("TERMINATE")
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)
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)
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)
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)
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fsm.act("CHECK_READ",
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If(sink.rcount > 0,
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If(sink.stb,
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sink.ack.eq(1),
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base_addr.ce.eq(1),
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NextState("READ_DATA")
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)
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).Else(
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NextState("IDLE")
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)
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)
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fsm.act("READ_DATA",
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bus.adr.eq(self.sink.data),
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bus.sel.eq(0xf),
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bus.stb.eq(1),
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bus.we.eq(0),
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bus.cyc.eq(1),
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If(bus.stb & bus.ack,
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sink.ack.eq(1),
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counter.ce.eq(1),
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fifo.sink.stb.eq(1),
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fifo.sink.sop.eq(counter == 0),
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fifo.sink.data.eq(bus.dat_r),
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If(counter.value == sink.rcount-1,
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fifo.sink.eop.eq(1),
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NextState("PRESENT_DATA")
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)
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)
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)
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fsm.act("PRESENT_DATA",
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source.stb.eq(fifo.stb),
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source.sop.eq(fifo.sop),
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source.eop.eq(fifo.eop),
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fifo.ack.eq(source.ack),
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source.length.eq(sink.rcount+1),
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source.wcount.eq(sink.rcount),
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source.rcount.eq(0),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthEtherbone(Module):
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def __init__(self, udp, udp_port):
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self.submodules.tx = tx = LiteEthEtherboneTX(udp_port)
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self.submodules.rx = rx = LiteEthEtherboneRX()
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udp_port = udp.crossbar.get_port(udp_port)
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self.comb += [
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Record.connect(tx.source, udp_port.sink),
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Record.connect(udp_port.source, rx.sink)
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]
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self.master = master = LiteEthEtherboneWishboneMaster()
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self.comb += [
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Record.connect(rx.source.connect(master.sink)),
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Record.connect(master.source.connect(tx.sink))
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]
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