220 lines
6.6 KiB
Python
220 lines
6.6 KiB
Python
from liteeth.common import *
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from liteeth.generic.depacketizer import LiteEthDepacketizer
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from liteeth.generic.packetizer import LiteEthPacketizer
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from liteeth.core.ip.crossbar import LiteEthIPV4Crossbar
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class LiteEthIPV4Depacketizer(LiteEthDepacketizer):
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def __init__(self):
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LiteEthDepacketizer.__init__(self,
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eth_mac_description(8),
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eth_ipv4_description(8),
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPV4Packetizer(LiteEthPacketizer):
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def __init__(self):
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LiteEthPacketizer.__init__(self,
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eth_ipv4_description(8),
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eth_mac_description(8),
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ipv4_header,
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ipv4_header_len)
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class LiteEthIPV4Checksum(Module):
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def __init__(self, words_per_clock_cycle=1, skip_checksum=False):
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self.reset = Signal() # XXX FIXME InsertReset generates incorrect verilog
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self.ce = Signal() # XXX FIXME InsertCE generates incorrect verilog
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self.header = Signal(ipv4_header_len*8)
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self.value = Signal(16)
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self.done = Signal()
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###
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s = Signal(17)
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r = Signal(17)
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n_cycles = 0
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for i in range(ipv4_header_len//2):
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if skip_checksum and (i == ipv4_header["checksum"].byte//2):
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pass
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else:
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s_next = Signal(17)
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r_next = Signal(17)
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self.comb += s_next.eq(r + self.header[i*16:(i+1)*16])
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r_next_eq = r_next.eq(Cat(s_next[:16]+s_next[16], Signal()))
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if (i%words_per_clock_cycle) != 0:
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self.comb += r_next_eq
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else:
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self.sync += \
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If(self.reset,
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r_next.eq(0)
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).Elif(self.ce & ~self.done,
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r_next_eq
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)
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n_cycles += 1
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s, r = s_next, r_next
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self.comb += self.value.eq(~Cat(r[8:16], r[:8]))
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if not skip_checksum:
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n_cycles += 1
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self.submodules.counter = counter = Counter(max=n_cycles+1)
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self.comb += [
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counter.reset.eq(self.reset),
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counter.ce.eq(self.ce & ~self.done),
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self.done.eq(counter.value == n_cycles)
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]
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class LiteEthIPTX(Module):
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def __init__(self, mac_address, ip_address, arp_table):
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self.sink = sink = Sink(eth_ipv4_user_description(8))
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self.source = source = Source(eth_mac_description(8))
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self.target_unreachable = Signal()
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###
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self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
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self.comb += [
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checksum.ce.eq(sink.stb & sink.sop),
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checksum.reset.eq(source.stb & source.eop & source.ack)
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]
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self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
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self.comb += [
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packetizer.sink.stb.eq(sink.stb & checksum.done),
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packetizer.sink.sop.eq(sink.sop),
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packetizer.sink.eop.eq(sink.eop),
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sink.ack.eq(packetizer.sink.ack & checksum.done),
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packetizer.sink.target_ip.eq(sink.ip_address),
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packetizer.sink.protocol.eq(sink.protocol),
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packetizer.sink.total_length.eq(sink.length + (0x5*4)),
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packetizer.sink.version.eq(0x4), # ipv4
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packetizer.sink.ihl.eq(0x5), # 20 bytes
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packetizer.sink.identification.eq(0),
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packetizer.sink.ttl.eq(0x80),
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packetizer.sink.sender_ip.eq(ip_address),
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packetizer.sink.data.eq(sink.data),
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checksum.header.eq(packetizer.header),
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packetizer.sink.checksum.eq(checksum.value)
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]
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target_mac = Signal(48)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.sop,
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packetizer.source.ack.eq(0),
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NextState("SEND_MAC_ADDRESS_REQUEST")
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)
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)
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self.comb += arp_table.request.ip_address.eq(sink.ip_address)
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fsm.act("SEND_MAC_ADDRESS_REQUEST",
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arp_table.request.stb.eq(1),
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If(arp_table.request.stb & arp_table.request.ack,
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NextState("WAIT_MAC_ADDRESS_RESPONSE")
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)
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)
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fsm.act("WAIT_MAC_ADDRESS_RESPONSE",
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If(arp_table.response.stb,
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arp_table.response.ack.eq(1),
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If(arp_table.response.failed,
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self.target_unreachable.eq(1),
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NextState("DROP"),
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).Else(
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NextState("SEND")
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)
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)
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)
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self.sync += \
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If(arp_table.response.stb,
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target_mac.eq(arp_table.response.mac_address)
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)
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fsm.act("SEND",
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Record.connect(packetizer.source, source),
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source.ethernet_type.eq(ethernet_type_ip),
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source.target_mac.eq(target_mac),
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source.sender_mac.eq(mac_address),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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packetizer.source.ack.eq(1),
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If(packetizer.source.stb & packetizer.source.eop & packetizer.source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthIPRX(Module):
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def __init__(self, mac_address, ip_address):
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self.sink = sink = Sink(eth_mac_description(8))
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self.source = source = Source(eth_ipv4_user_description(8))
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###
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self.submodules.depacketizer = depacketizer = LiteEthIPV4Depacketizer()
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self.comb += Record.connect(sink, depacketizer.sink)
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self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=False)
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self.comb += [
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checksum.header.eq(depacketizer.header),
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checksum.reset.eq(depacketizer.source.stb & depacketizer.source.eop),
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checksum.ce.eq(depacketizer.source.stb & depacketizer.source.sop)
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]
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.sop,
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depacketizer.source.ack.eq(0),
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NextState("CHECK")
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)
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)
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valid = Signal()
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self.sync += valid.eq(
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depacketizer.source.stb &
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(depacketizer.source.target_ip == ip_address) &
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(depacketizer.source.version == 0x4) &
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(depacketizer.source.ihl == 0x5) &
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(checksum.value == 0)
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)
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fsm.act("CHECK",
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If(checksum.done,
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If(valid,
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NextState("PRESENT")
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).Else(
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NextState("DROP")
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)
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)
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)
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self.comb += [
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source.sop.eq(depacketizer.source.sop),
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source.eop.eq(depacketizer.source.eop),
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source.length.eq(depacketizer.source.total_length - (0x5*4)),
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source.protocol.eq(depacketizer.source.protocol),
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source.ip_address.eq(depacketizer.source.sender_ip),
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source.data.eq(depacketizer.source.data),
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source.error.eq(depacketizer.source.error)
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]
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fsm.act("PRESENT",
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source.stb.eq(depacketizer.source.stb),
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depacketizer.source.ack.eq(source.ack),
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If(source.stb & source.eop & source.ack,
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NextState("IDLE")
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)
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)
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fsm.act("DROP",
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depacketizer.source.ack.eq(1),
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If(depacketizer.source.stb & depacketizer.source.eop & depacketizer.source.ack,
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NextState("IDLE")
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)
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)
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class LiteEthIP(Module):
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def __init__(self, mac, mac_address, ip_address, arp_table):
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self.submodules.tx = tx = LiteEthIPTX(mac_address, ip_address, arp_table)
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self.submodules.rx = rx = LiteEthIPRX(mac_address, ip_address)
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mac_port = mac.crossbar.get_port(ethernet_type_ip)
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self.comb += [
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Record.connect(tx.source, mac_port.sink),
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Record.connect(mac_port.source, rx.sink)
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]
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self.submodules.crossbar = crossbar = LiteEthIPV4Crossbar()
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self.comb += [
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Record.connect(crossbar.master.source, tx.sink),
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Record.connect(rx.source, crossbar.master.sink)
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]
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