134 lines
4.8 KiB
Plaintext
134 lines
4.8 KiB
Plaintext
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/ / (_) /____ / __/______ ___ ___
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/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
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/____/_/\__/\__/___/\__/\___/ .__/\__/
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/_/
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Copyright 2012-2015 / EnjoyDigital / M-Labs Ltd
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A small footprint and configurable embedded FPGA
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logic analyzer core powered by Migen
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[> Doc
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---------
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HTML : www.enjoy-digital.fr/litescope/
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PDF : www.enjoy-digital.fr/litescope.pdf
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[> Intro
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---------
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LiteScope is a small footprint and configurable embedded logic analyzer that you
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can use in your FPGA and aims to provide a free, portable and flexible
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alternative to vendor's solutions!
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LiteScope is part of MiSoC libraries whose aims are to lower entry level of complex
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FPGA cores by providing simple, elegant and efficient implementations of
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components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
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The core uses simple and specific streaming buses and will provides in the future
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adapters to use standardized AXI or Avalon-ST streaming buses.
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Since Python is used to describe the HDL, the core is highly and easily
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configurable.
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LiteScope uses technologies developed in partnership with M-Labs Ltd:
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- Migen enables generating HDL with Python in an efficient way.
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- MiSoC provides the basic blocks to build a powerful and small footprint SoC.
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LiteScope can be used as a Migen/MiSoC library (by simply installing it
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with the provided setup.py) or can be integrated with your standard design flow
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by generating the verilog rtl that you will use as a standard core.
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LiteScope handles various export formats: .vcd, .sr(sigrok), .csv, .py...
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Since LiteScope also provides a UART <--> Wishbone brige so you only need 2
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external Rx/Tx pins to be ready to debug or control all your Wishbone peripherals!
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[> Features
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-----------
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- IO peek and poke with LiteScopeIO
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- Logic analyser with LiteScopeLA:
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- Various triggering modules: Term, Range, Edge (add yours! :)
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- Run Length Encoder to "compress" data and increase recording depth
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- Subsampling
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- Storage qualifier
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- Data storage in block rams
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- Bridges:
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- UART2Wishbone (provided by LiteScope)
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- Ethernet2Wishbone ("Etherbone") (when used with LiteEth)
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[> Possible improvements
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-------------------------
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- add standardized interfaces (AXI, Avalon-ST)
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- add protocols analyzers
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- add signals injection/generation
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- add storage in DRAM
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- add storage in HDD with LiteSATA core (to be released soon!)
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- add PCIe Wishbone bridge with LitePCIe (to be released soon!)
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- ... See below Support and consulting :)
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If you want to support these features, please contact us at florent [AT]
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enjoy-digital.fr. You can also contact our partner on the public mailing list
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devel [AT] lists.m-labs.hk.
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[> Getting started
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------------------
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1. Install Python3 and your vendor's software
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2. Obtain Migen and install it:
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git clone https://github.com/m-labs/migen
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cd migen
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python3 setup.py install
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cd ..
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3. Obtain MiSoC:
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git clone https://github.com/m-labs/misoc --recursive
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4. Build and load test design:
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go to misoclib/tools/litescope/example_designs/
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./make.py -p [your_platform] all load-bitstream
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Supported platforms are the ones already supported by Mibuild:
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de0nano, m1, mixxeo, kc705, zedboard...
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5. Test design:
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go to [..]/example_designs/test/ and run:
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./make.py --port your_serial_port test_io (will blink leds)
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./make.py --port your_serial_port test_la (will capture counter)
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tests can also be executed over Etherbone (provided with LiteEth):
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./make.py --ip_address fpga_ip_address test_io
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./make.py --ip_address fpga_ip_address test_la
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[> Simulations:
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XXX convert simulations
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[> Tests :
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XXX convert tests
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[> License
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-----------
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LiteScope is released under the very permissive two-clause BSD license. Under the
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terms of this license, you are authorized to use LiteScope for closed-source
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proprietary designs.
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Even though we do not require you to do so, those things are awesome, so please
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do them if possible:
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- tell us that you are using LiteScope
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- cite LiteScope in publications related to research it has helped
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- send us feedback and suggestions for improvements
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- send us bug reports when something goes wrong
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- send us the modifications and improvements you have done to LiteScope.
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[> Support and consulting
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--------------------------
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We love open-source hardware and like sharing our designs with others.
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LiteScope is mainly developed and maintained by EnjoyDigital.
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If you would like to know more about LiteScope or if you are already a happy user
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and would like to extend it for your needs, EnjoyDigital can provide standard
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commercial support as well as consulting services.
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So feel free to contact us, we'd love to work with you! (and eventually shorten
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the list of the possible improvements :)
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[> Contact
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E-mail: florent [AT] enjoy-digital.fr |