113 lines
2.3 KiB
Python
113 lines
2.3 KiB
Python
from migen.fhdl.std import *
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from migen.genlib.misc import optree
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class CRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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d : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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"""
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def __init__(self, dat_width, width, polynom):
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self.d = Signal(dat_width)
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self.last = Signal(width)
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self.next = Signal(width)
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###
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def _optimize_eq(l):
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"""
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Replace even numbers of XORs in the equation
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with an equivalent XOR
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"""
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d = {}
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# compute and optimize CRC's LFSR
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curval = [[("state", i)] for i in range(width)]
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for i in range(dat_width):
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feedback = curval.pop() + [("din", i)]
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curval.insert(0, feedback)
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for j in range(1, width-1):
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if (polynom&(1<<j)):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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# implement logic
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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if t == "state":
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xors += [self.last[n]]
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elif t == "din":
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xors += [self.d[n]]
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self.comb += self.next[i].eq(optree("^", xors))
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class CRC32(Module):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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Attributes
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----------
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d : in
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Data input.
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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check = 0xC704DD7B
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def __init__(self, dat_width):
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self.d = Signal(dat_width)
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self.value = Signal(self.width)
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self.error = Signal()
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###
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self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
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reg = Signal(self.width, reset=2**self.width-1)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.d.eq(self.d),
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self.engine.last.eq(reg),
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self.value.eq(~reg[::-1]),
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self.error.eq(reg != self.check)
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]
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