Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
litex/targets
History
Florent Kermarrec b2f32ad124 targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00
..
__init__.py add support for external platforms and targets 2013-11-24 16:55:33 +01:00
de0nano.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
kc705.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
mlabs_video.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
pipistrello.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
ppro.py soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
simple.py targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00