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72 lines
2.9 KiB
Python
72 lines
2.9 KiB
Python
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019 Gabriel L. Somlo <somlo@cmu.edu>
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# License: BSD
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####################################################################################################
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# DISCLAIMER: Provides retro-compatibility layer for existing SoCSDRAM based designs.
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# Most of the SoC code has been refactored/improved and is now located in integration/soc.py
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####################################################################################################
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import inspect
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from migen import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc import auto_int
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__all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
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# SoCSDRAM -----------------------------------------------------------------------------------------
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class SoCSDRAM(SoCCore):
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def __init__(self, platform, clk_freq,
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l2_size = 8192,
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l2_reverse = True,
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min_l2_data_width = 128,
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max_sdram_size = None,
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**kwargs):
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SoCCore.__init__(self, platform, clk_freq, **kwargs)
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self.l2_size = l2_size
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self.l2_reverse = l2_reverse
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self.min_l2_data_width = min_l2_data_width
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self.max_sdram_size = max_sdram_size
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def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
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class _SDRAMModule: pass
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module = _SDRAMModule()
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module.geom_settings = geom_settings
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module.timing_settings = timing_settings
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self.add_sdram("sdram",
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phy = phy,
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module = module,
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origin = self.mem_map["main_ram"],
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size = self.max_sdram_size,
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l2_cache_size = self.l2_size,
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l2_cache_min_data_width = self.min_l2_data_width,
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l2_cache_reverse = self.l2_reverse,
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**kwargs,
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)
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# SoCSDRAM arguments --------------------------------------------------------------------------------
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def soc_sdram_args(parser):
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soc_core_args(parser)
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# L2 Cache
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parser.add_argument("--l2-size", default=8192, type=auto_int,
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help="L2 cache size (default=8192)")
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parser.add_argument("--min-l2-data-width", default=128, type=auto_int,
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help="Minimum L2 cache datawidth (default=128)")
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# SDRAM
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parser.add_argument("--max-sdram-size", default=0x40000000, type=auto_int,
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help="Maximum SDRAM size mapped to the SoC (default=1GB))")
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def soc_sdram_argdict(args):
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r = soc_core_argdict(args)
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for a in inspect.getargspec(SoCSDRAM.__init__).args:
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if a not in ["self", "platform", "clk_freq"]:
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arg = getattr(args, a, None)
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if arg is not None:
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r[a] = arg
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return r
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