81 lines
2.7 KiB
C
81 lines
2.7 KiB
C
/*
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* Milkymist SoC (Software)
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* Copyright (C) 2012 Sebastien Bourdeauducq
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HW_DFII_H
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#define __HW_DFII_H
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#include <hw/common.h>
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#include <csrbase.h>
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#define DFII_CSR(x) MMPTR(DFII_BASE+(x))
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#define CSR_DFII_CONTROL DFII_CSR(0x00)
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#define DFII_CONTROL_SEL 0x01
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#define DFII_CONTROL_CKE 0x02
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#define CSR_DFII_COMMAND_P0 DFII_CSR(0x04)
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#define CSR_DFII_AH_P0 DFII_CSR(0x08)
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#define CSR_DFII_AL_P0 DFII_CSR(0x0C)
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#define CSR_DFII_BA_P0 DFII_CSR(0x10)
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#define CSR_DFII_WD0_P0 DFII_CSR(0x14)
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#define CSR_DFII_WD1_P0 DFII_CSR(0x18)
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#define CSR_DFII_WD2_P0 DFII_CSR(0x1C)
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#define CSR_DFII_WD3_P0 DFII_CSR(0x20)
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#define CSR_DFII_WD4_P0 DFII_CSR(0x24)
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#define CSR_DFII_WD5_P0 DFII_CSR(0x28)
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#define CSR_DFII_WD6_P0 DFII_CSR(0x2C)
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#define CSR_DFII_WD7_P0 DFII_CSR(0x30)
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#define CSR_DFII_RD0_P0 DFII_CSR(0x34)
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#define CSR_DFII_RD1_P0 DFII_CSR(0x38)
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#define CSR_DFII_RD2_P0 DFII_CSR(0x3C)
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#define CSR_DFII_RD3_P0 DFII_CSR(0x40)
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#define CSR_DFII_RD4_P0 DFII_CSR(0x44)
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#define CSR_DFII_RD5_P0 DFII_CSR(0x48)
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#define CSR_DFII_RD6_P0 DFII_CSR(0x4C)
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#define CSR_DFII_RD7_P0 DFII_CSR(0x50)
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#define CSR_DFII_COMMAND_P1 DFII_CSR(0x54)
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#define CSR_DFII_AH_P1 DFII_CSR(0x58)
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#define CSR_DFII_AL_P1 DFII_CSR(0x5C)
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#define CSR_DFII_BA_P1 DFII_CSR(0x60)
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#define CSR_DFII_WD0_P1 DFII_CSR(0x64)
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#define CSR_DFII_WD1_P1 DFII_CSR(0x68)
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#define CSR_DFII_WD2_P1 DFII_CSR(0x6C)
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#define CSR_DFII_WD3_P1 DFII_CSR(0x70)
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#define CSR_DFII_WD4_P1 DFII_CSR(0x74)
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#define CSR_DFII_WD5_P1 DFII_CSR(0x78)
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#define CSR_DFII_WD6_P1 DFII_CSR(0x7C)
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#define CSR_DFII_WD7_P1 DFII_CSR(0x80)
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#define CSR_DFII_RD0_P1 DFII_CSR(0x84)
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#define CSR_DFII_RD1_P1 DFII_CSR(0x88)
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#define CSR_DFII_RD2_P1 DFII_CSR(0x8C)
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#define CSR_DFII_RD3_P1 DFII_CSR(0x90)
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#define CSR_DFII_RD4_P1 DFII_CSR(0x94)
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#define CSR_DFII_RD5_P1 DFII_CSR(0x98)
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#define CSR_DFII_RD6_P1 DFII_CSR(0x9C)
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#define CSR_DFII_RD7_P1 DFII_CSR(0xA0)
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#define DFII_COMMAND_CS 0x01
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#define DFII_COMMAND_WE 0x02
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#define DFII_COMMAND_CAS 0x04
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#define DFII_COMMAND_RAS 0x08
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#define DFII_COMMAND_WRDATA 0x10
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#define DFII_COMMAND_RDDATA 0x20
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#endif /* __HW_DFII_H */
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