litex/migen/corelogic
Sebastien Bourdeauducq d8e478efee Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
..
__init__.py corelogic: round-robin module 2011-12-08 21:15:02 +01:00
buffers.py New specification for width and signedness 2012-11-29 21:22:38 +01:00
divider.py Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
fsm.py New specification for width and signedness 2012-11-29 21:22:38 +01:00
misc.py Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00
record.py New specification for width and signedness 2012-11-29 21:22:38 +01:00
roundrobin.py Replace Signal(bits_for(... with Signal(max=... 2012-11-29 21:53:36 +01:00