75 lines
2.1 KiB
Python
75 lines
2.1 KiB
Python
from migen.fhdl.structure import *
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class RegisterRaw:
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def __init__(self, name, size=1):
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self.name = name
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self.size = size
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self.re = Signal()
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self.r = Signal(BV(self.size))
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self.w = Signal(BV(self.size))
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(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
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class Field:
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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self.name = name
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self.size = size
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self.access_bus = access_bus
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self.access_dev = access_dev
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self.storage = Signal(BV(self.size), reset=reset)
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if self.access_dev == READ_ONLY or self.access_dev == READ_WRITE:
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self.r = Signal(BV(self.size))
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if self.access_dev == WRITE_ONLY or self.access_dev == READ_WRITE:
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self.w = Signal(BV(self.size))
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self.we = Signal()
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class RegisterFields:
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def __init__(self, name, fields):
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self.name = name
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self.fields = fields
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class RegisterField(RegisterFields):
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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self.field = Field(name, size, access_bus, access_dev, reset)
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RegisterFields.__init__(self, name, [self.field])
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class FieldAlias:
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def __init__(self, f, start, end):
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self.size = end - start
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self.access_bus = f.access_bus
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self.access_dev = f.access_dev
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self.storage = f.storage[start:end]
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# device access is through the original field
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def expand_description(description, busword):
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d = []
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for reg in description:
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if isinstance(reg, RegisterRaw):
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if reg.size > busword:
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raise ValueError("Raw register larger than a bus word")
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d.append(reg)
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elif isinstance(reg, RegisterFields):
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f = []
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size = 0
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for field in reg.fields:
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size += field.size
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if size > busword:
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top = field.size
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while size > busword:
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slice1 = busword - size + top
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slice2 = min(size - busword, busword)
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if slice1:
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f.append(FieldAlias(field, top - slice1, top))
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top -= slice1
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d.append(RegisterFields(reg.name, f))
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f = [FieldAlias(field, top - slice2, top)]
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top -= slice2
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size -= busword
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else:
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f.append(field)
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if f:
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d.append(RegisterFields(reg.name, f))
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else:
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raise TypeError
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return d
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