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litex
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migen
History
Sebastien Bourdeauducq
26e0b817e8
verilog: ignore variable property in combinatorial block
2011-12-21 23:00:36 +01:00
..
bank
Remove uses of declare_signal
2011-12-18 21:47:48 +01:00
bus
Remove uses of declare_signal
2011-12-18 21:47:48 +01:00
corelogic
corelogic: fix signal exports
2011-12-18 21:54:28 +01:00
fhdl
verilog: ignore variable property in combinatorial block
2011-12-21 23:00:36 +01:00
__init__.py
Initial import, FHDL basic structure, divider example
2011-12-04 16:44:38 +01:00