201 lines
6.4 KiB
Python
201 lines
6.4 KiB
Python
from operator import itemgetter
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import re
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from migen.fhdl.std import *
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from migen.bank.description import CSRStatus
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def get_macros(filename):
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f = open(filename, "r")
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r = {}
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for line in f:
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match = re.match("\w*#define\s+(\w+)\s+(.*)", line, re.IGNORECASE)
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if match:
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r[match.group(1)] = match.group(2)
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return r
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def _get_rw_functions(reg_name, reg_base, size, read_only):
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r = ""
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if size > 8:
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raise NotImplementedError("Register too large")
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elif size > 4:
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ctype = "unsigned long long int"
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elif size > 2:
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ctype = "unsigned int"
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elif size > 1:
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ctype = "unsigned short int"
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else:
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ctype = "unsigned char"
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r += "static inline "+ctype+" "+reg_name+"_read(void) {\n"
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if size > 1:
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r += "\t"+ctype+" r = MMPTR("+hex(reg_base)+");\n"
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for byte in range(1, size):
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r += "\tr <<= 8;\n\tr |= MMPTR("+hex(reg_base+4*byte)+");\n"
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r += "\treturn r;\n}\n"
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else:
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r += "\treturn MMPTR("+hex(reg_base)+");\n}\n"
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if not read_only:
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r += "static inline void "+reg_name+"_write("+ctype+" value) {\n"
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for byte in range(size):
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shift = (size-byte-1)*8
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if shift:
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value_shifted = "value >> "+str(shift)
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else:
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value_shifted = "value"
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r += "\tMMPTR("+hex(reg_base+4*byte)+") = "+value_shifted+";\n"
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r += "}\n"
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return r
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def get_csr_header(csr_base, bank_array, interrupt_map):
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r = "#ifndef __HW_CSR_H\n#define __HW_CSR_H\n#include <hw/common.h>\n"
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for name, csrs, mapaddr, rmap in bank_array.banks:
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r += "\n/* "+name+" */\n"
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reg_base = csr_base + 0x800*mapaddr
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r += "#define "+name.upper()+"_BASE "+hex(reg_base)+"\n"
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for csr in csrs:
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nr = (csr.size + 7)//8
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r += _get_rw_functions(name + "_" + csr.name, reg_base, nr, isinstance(csr, CSRStatus))
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reg_base += 4*nr
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try:
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interrupt_nr = interrupt_map[name]
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except KeyError:
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pass
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else:
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r += "#define "+name.upper()+"_INTERRUPT "+str(interrupt_nr)+"\n"
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r += "\n#endif\n"
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return r
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def get_sdram_phy_header(sdram_phy):
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if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
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raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
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r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
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r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
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r += "static void cdelay(int i);\n"
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#
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# commands_px functions
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#
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for n in range(sdram_phy.phy_settings.nphases):
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r += """
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static void command_p{n}(int cmd)
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{{
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dfii_pi{n}_command_write(cmd);
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dfii_pi{n}_command_issue_write(1);
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}}""".format(n=str(n))
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r += "\n\n"
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#
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# rd/wr access macros
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#
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r += """
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#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
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#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
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#define dfii_pird_baddress_write(X) dfii_pi{rdphase}_baddress_write(X)
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#define dfii_piwr_baddress_write(X) dfii_pi{wrphase}_baddress_write(X)
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#define command_prd(X) command_p{rdphase}(X)
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#define command_pwr(X) command_p{wrphase}(X)
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""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
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r +="\n"
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#
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# init sequence
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#
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cmds = {
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"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
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"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
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"CKE" : "DFII_CONTROL_CKE"
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}
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def gen_cmd(comment, a, ba, cmd, delay):
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r = "\t/* %s */\n" %comment
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r += "\tdfii_pi0_address_write(0x%04X);\n" %a
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r += "\tdfii_pi0_baddress_write(%d);\n" %ba
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if "CKE" in cmd:
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r += "\tdfii_control_write(%s);\n" %cmd
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else:
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r += "\tcommand_p0(%s);\n" %cmd
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r += "\tcdelay(%d);\n" %delay
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r += "\n"
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return r
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r += "static void init_sequence(void)\n{\n"
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cl = sdram_phy.phy_settings.cl
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if sdram_phy.phy_settings.type == "SDR":
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bl = 1*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "LPDDR":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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elif sdram_phy.phy_settings.type == "DDR2":
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bl = 2*sdram_phy.phy_settings.nphases
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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reset_dll = 1 << 8
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init_sequence = [
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register / Reset DLL, CL=%d, BL=%d" %(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
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("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
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("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
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("Load Mode Register / CL=%d, BL=%d" %(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
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]
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for comment, a, ba, cmd, delay in init_sequence:
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r += gen_cmd(comment, a, ba, cmd, delay)
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r += "}\n"
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r += "#endif\n"
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return r
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