51 lines
1.5 KiB
Python
51 lines
1.5 KiB
Python
from migen.fhdl.structure import *
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from migen.fhdl import verilog
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class LM32:
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def __init__(self):
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self.inst = Instance("lm32_top",
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Instance.ClockPort("clk_i"),
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Instance.ResetPort("rst_i"),
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Instance.Input("interrupt", BV(32)),
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Instance.Input("ext_break", BV(1)),
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Instance.Output("I_ADR_O", BV(32)),
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Instance.Output("I_DAT_O", BV(32)),
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Instance.Output("I_SEL_O", BV(4)),
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Instance.Output("I_CYC_O", BV(1)),
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Instance.Output("I_STB_O", BV(1)),
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Instance.Output("I_WE_O", BV(1)),
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Instance.Output("I_CTI_O", BV(3)),
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Instance.Output("I_LOCK_O", BV(1)),
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Instance.Output("I_BTE_O", BV(1)),
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Instance.Input("I_DAT_I", BV(32)),
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Instance.Input("I_ACK_I", BV(1)),
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Instance.Input("I_ERR_I", BV(1)),
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Instance.Input("I_RTY_I", BV(1)),
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Instance.Output("D_ADR_O", BV(32)),
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Instance.Output("D_DAT_O", BV(32)),
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Instance.Output("D_SEL_O", BV(4)),
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Instance.Output("D_CYC_O", BV(1)),
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Instance.Output("D_STB_O", BV(1)),
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Instance.Output("D_WE_O", BV(1)),
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Instance.Output("D_CTI_O", BV(3)),
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Instance.Output("D_LOCK_O", BV(1)),
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Instance.Output("D_BTE_O", BV(1)),
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Instance.Input("D_DAT_I", BV(32)),
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Instance.Input("D_ACK_I", BV(1)),
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Instance.Input("D_ERR_I", BV(1)),
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Instance.Input("D_RTY_I", BV(1)),
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name="lm32")
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def get_fragment(self):
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return Fragment(instances=[self.inst])
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cpus = [LM32() for i in range(4)]
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frag = Fragment()
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for cpu in cpus:
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frag += cpu.get_fragment()
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print(verilog.convert(frag, set([cpus[0].inst.get_io("interrupt"), cpus[0].inst.get_io("I_WE_O")])))
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