80 lines
1.8 KiB
Python
80 lines
1.8 KiB
Python
from migen.flow.network import *
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from migen.actorlib.sim import *
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from migen.bus import wishbone
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from migen.bus.transactions import *
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from migen.uio.ioo import UnifiedIOSimulation
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from migen.pytholite.transel import Register
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from migen.pytholite.compiler import make_pytholite
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from migen.sim.generic import Simulator
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from migen.sim.icarus import Runner
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from migen.fhdl import verilog
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layout = [("r", BV(32))]
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def gen():
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ds = Register(32)
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for i in range(3):
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r = TRead(i, busname="mem")
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yield r
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ds.store = r.data
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yield Token("result", {"r": ds})
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for i in range(5):
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r = TRead(i, busname="wb")
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yield r
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ds.store = r.data
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yield Token("result", {"r": ds})
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class Dumper(SimActor):
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def __init__(self):
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def dumper_gen():
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while True:
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t = Token("result")
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yield t
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print(t.value["r"])
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super().__init__(dumper_gen(),
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("result", Sink, layout))
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class SlaveModel(wishbone.TargetModel):
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def read(self, address):
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return address + 4
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def run_sim(ng):
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g = DataFlowGraph()
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d = Dumper()
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g.add_connection(ActorNode(ng), ActorNode(d))
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slave = wishbone.Target(SlaveModel())
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intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)
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c = CompositeActor(g)
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fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
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sim = Simulator(fragment, Runner())
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sim.run(50)
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del sim
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def main():
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mem = Memory(32, 3, init=[42, 37, 81])
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dataflow = [("result", Source, layout)]
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buses = {
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"wb": wishbone.Interface(),
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"mem": mem
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}
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print("Simulating native Python:")
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ng_native = UnifiedIOSimulation(gen(),
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dataflow=dataflow,
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buses=buses)
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run_sim(ng_native)
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print("Simulating Pytholite:")
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ng_pytholite = make_pytholite(gen,
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dataflow=dataflow,
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buses=buses)
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run_sim(ng_pytholite)
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print("Converting Pytholite to Verilog:")
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print(verilog.convert(ng_pytholite.get_fragment()))
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main()
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