116 lines
3.2 KiB
Python
116 lines
3.2 KiB
Python
################################################################################
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# _____ _ ____ _ _ _ _
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# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
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# | __| | | | . | | | | | | | . | | _| .'| |
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# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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# |___| |___| |___|
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#
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# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# miscope example on De0 Nano
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# --------------------------------
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################################################################################
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from migen.fhdl.std import *
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from migen.bus import csr
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from migen.bank import csrgen
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from miscope.std.misc import *
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from miscope.trigger import Term, RangeDetector, EdgeDetector, Sum, Trigger
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from miscope.storage import Recorder
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from miscope.miio import MiIo
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from miscope.mila import MiLa
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from miscope.com import uart2csr
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from timings import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Timings Param
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clk_freq = 50*MHz
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# Mila Param
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trig_w = 16
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dat_w = 16
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rec_size = 4096
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#==============================================================================
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# M I S C O P E E X A M P L E
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#==============================================================================
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class SoC(Module):
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csr_base = 0xe0000000
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csr_map = {
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"miio": 1,
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"mila": 2,
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}
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def __init__(self, platform):
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# MiIo
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self.submodules.miio = MiIo(8)
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# MiLa
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term = Term(trig_w)
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trigger = Trigger(trig_w, [term])
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recorder = Recorder(dat_w, rec_size)
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self.submodules.mila = MiLa(trigger, recorder)
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# Uart2Csr
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self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
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uart_pads = platform.request("serial")
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self.comb += uart_pads.tx.eq(self.uart2csr.tx)
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self.comb += self.uart2csr.rx.eq(uart_pads.rx)
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# Csr Interconnect
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self.submodules.csrbankarray = csrgen.BankArray(self,
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lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override])
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self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr, self.csrbankarray.get_buses())
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# Led
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self.led = Cat(*[platform.request("user_led", i) for i in range(8)])
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# Misc
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self.cnt = Signal(9)
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self.submodules.freqgen = FreqGen(clk_freq, 500*KHz)
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self.submodules.eventgen_rising = EventGen(RISING_EDGE, clk_freq, 100*ns)
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self.submodules.eventgen_falling = EventGen(FALLING_EDGE, clk_freq, 100*ns)
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self.comb += [
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self.eventgen_rising.i.eq(self.freqgen.o),
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self.eventgen_falling.i.eq(self.freqgen.o)
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]
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###
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#
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# Miio
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#
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# Output
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self.comb += self.led.eq(self.miio.o)
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# Input
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self.comb += self.miio.i.eq(self.miio.o)
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#
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# Mila
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#
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self.comb +=[
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self.mila.sink.stb.eq(1),
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self.mila.sink.dat.eq(Cat(
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self.freqgen.o,
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self.eventgen_rising.o,
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self.eventgen_falling.o,
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self.cnt)
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)
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]
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self.sync += self.cnt.eq(self.cnt+1)
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