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https://github.com/enjoy-digital/litex.git
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908 lines
36 KiB
Python
908 lines
36 KiB
Python
# This file is Copyright (c) 2018-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2019 Michael Betz <michibetz@gmail.com>
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# License: BSD
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"""Clock Abstraction Modules"""
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import math
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import logging
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.io import DifferentialInput
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from litex.soc.integration.soc import colorer
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from litex.soc.interconnect.csr import *
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logging.basicConfig(level=logging.INFO)
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def period_ns(freq):
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return 1e9/freq
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# Logging ------------------------------------------------------------------------------------------
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def register_clkin_log(logger, clkin, freq):
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logger.info("Registering {} {} of {}.".format(
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colorer("Differential") if isinstance(clkin, Record) else colorer("Single Ended"),
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colorer("ClkIn"),
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colorer("{:3.2f}MHz".format(freq/1e6))
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))
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def create_clkout_log(logger, name, freq, margin, nclkouts):
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logger.info("Creating {} of {} {}.".format(
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colorer("ClkOut{} {}".format(nclkouts, name)),
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colorer("{:3.2f}MHz".format(freq/1e6)),
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"(+-{:3.2f}ppm)".format(margin*1e6),
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))
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def compute_config_log(logger, config):
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log = "Config:\n"
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length = 0
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for name in config.keys():
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if len(name) > length: length = len(name)
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for name, value in config.items():
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if "freq" in name or "vco" in name:
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value = "{:3.2f}MHz".format(value/1e6)
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if "phase" in name:
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value = "{:3.2f}°".format(value)
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log += "{}{}: {}\n".format(name, " "*(length-len(name)), value)
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log = log[:-1]
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logger.info(log)
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# Helpers ------------------------------------------------------------------------------------------
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def clkdiv_range(start, stop, step=1):
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start = float(start)
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stop = float(stop)
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step = float(step)
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current = start
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while current < stop:
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yield int(current) if math.floor(current) == current else current
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current += step
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# Xilinx / Generic ---------------------------------------------------------------------------------
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class XilinxClocking(Module, AutoCSR):
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clkfbout_mult_frange = (2, 64+1)
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clkout_divide_range = (1, 128+1)
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def __init__(self, vco_margin=0):
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.clkouts = {}
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self.config = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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self.clkin = Signal()
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if isinstance(clkin, (Signal, ClockSignal)):
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self.comb += self.clkin.eq(clkin)
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elif isinstance(clkin, Record):
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self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
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else:
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raise ValueError
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self.clkin_freq = freq
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register_clkin_log(self.logger, clkin, freq)
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def create_clkout(self, cd, freq, phase=0, buf="bufg", margin=1e-2, with_reset=True, ce=None):
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assert self.nclkouts < self.nclkouts_max
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clkout = Signal()
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self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
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if with_reset:
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self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset)
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if buf is None:
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self.comb += cd.clk.eq(clkout)
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else:
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clkout_buf = Signal()
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self.comb += cd.clk.eq(clkout_buf)
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if buf == "bufg":
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self.specials += Instance("BUFG", i_I=clkout, o_O=clkout_buf)
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elif buf == "bufr":
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self.specials += Instance("BUFR", i_I=clkout, o_O=clkout_buf)
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elif buf == "bufgce":
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if ce is None:
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raise ValueError("BUFGCE requires user to provide a clock enable ce Signal")
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self.specials += Instance("BUFGCE", i_I=clkout, o_O=clkout_buf, i_CE=ce)
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elif buf == "bufio":
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self.specials += Instance("BUFIO", i_I=clkout, o_O=clkout_buf)
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else:
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raise ValueError("Unsupported clock buffer: {}".format(buf))
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create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
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self.nclkouts += 1
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def compute_config(self):
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config = {}
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for divclk_divide in range(*self.divclk_divide_range):
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config["divclk_divide"] = divclk_divide
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for clkfbout_mult in reversed(range(*self.clkfbout_mult_frange)):
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all_valid = True
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vco_freq = self.clkin_freq*clkfbout_mult/divclk_divide
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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valid = False
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d_ranges = [self.clkout_divide_range]
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if getattr(self, "clkout{}_divide_range".format(n), None) is not None:
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d_ranges += [getattr(self, "clkout{}_divide_range".format(n))]
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for d_range in d_ranges:
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for d in clkdiv_range(*d_range):
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clk_freq = vco_freq/d
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if abs(clk_freq - f) <= f*m:
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config["clkout{}_freq".format(n)] = clk_freq
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config["clkout{}_divide".format(n)] = d
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config["clkout{}_phase".format(n)] = p
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valid = True
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break
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if valid:
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break
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if not valid:
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all_valid = False
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else:
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all_valid = False
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if all_valid:
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config["vco"] = vco_freq
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config["clkfbout_mult"] = clkfbout_mult
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compute_config_log(self.logger, config)
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return config
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raise ValueError("No PLL config found")
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def expose_drp(self):
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self.drp_reset = CSR()
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self.drp_locked = CSRStatus()
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self.drp_read = CSR()
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self.drp_write = CSR()
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self.drp_drdy = CSRStatus()
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self.drp_adr = CSRStorage(7, reset_less=True)
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self.drp_dat_w = CSRStorage(16, reset_less=True)
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self.drp_dat_r = CSRStatus(16)
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# # #
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den_pipe = Signal()
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dwe_pipe = Signal()
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drp_drdy = Signal()
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self.params.update(
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i_DCLK = ClockSignal(),
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i_DWE = dwe_pipe,
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i_DEN = den_pipe,
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o_DRDY = drp_drdy,
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i_DADDR = self.drp_adr.storage,
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i_DI = self.drp_dat_w.storage,
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o_DO = self.drp_dat_r.status
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)
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self.sync += [
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den_pipe.eq(self.drp_read.re | self.drp_write.re),
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dwe_pipe.eq(self.drp_write.re),
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If(self.drp_read.re | self.drp_write.re,
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self.drp_drdy.status.eq(0)
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).Elif(drp_drdy,
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self.drp_drdy.status.eq(1)
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)
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]
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self.comb += self.drp_locked.status.eq(self.locked)
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self.logger.info("Exposing DRP interface.")
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def do_finalize(self):
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assert hasattr(self, "clkin")
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# Xilinx / Spartan6 --------------------------------------------------------------------------------
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class S6PLL(XilinxClocking):
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nclkouts_max = 6
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clkin_freq_range = (19e6, 540e6)
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("S6PLL")
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self.logger.info("Creating S6PLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 52 + 1)
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self.vco_freq_range = {
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-1: (400e6, 1000e6),
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-2: (400e6, 1000e6),
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-3: (400e6, 1080e6),
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}[speedgrade]
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def do_finalize(self):
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XilinxClocking.do_finalize(self)
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config = self.compute_config()
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pll_fb = Signal()
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self.params.update(
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p_SIM_DEVICE = "SPARTAN6",
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p_BANDWIDTH = "OPTIMIZED",
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p_COMPENSATION = "INTERNAL",
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p_REF_JITTER = .01, p_CLK_FEEDBACK="CLKFBOUT",
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p_CLKIN1_PERIOD = 1e9/self.clkin_freq,
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p_CLKIN2_PERIOD = 0.,
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p_CLKFBOUT_MULT = config["clkfbout_mult"],
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p_CLKFBOUT_PHASE = 0.,
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p_DIVCLK_DIVIDE = config["divclk_divide"],
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i_CLKINSEL = 1,
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i_RST = self.reset,
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i_CLKIN1 = self.clkin,
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i_CLKFBIN = pll_fb,
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o_CLKFBOUT = pll_fb,
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o_LOCKED = self.locked,
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = float(config["clkout{}_phase".format(n)])
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self.params["p_CLKOUT{}_DUTY_CYCLE".format(n)] = 0.5
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLL_ADV", **self.params)
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class S6DCM(XilinxClocking):
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""" single output with f_out = f_in * {2 .. 256} / {1 .. 256} """
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nclkouts_max = 1
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clkfbout_mult_frange = (2, 256 + 1)
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clkout_divide_range = (1, 256 + 1)
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("S6DCM")
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self.logger.info("Creating S6DCM, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 2) # FIXME
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self.clkin_freq_range = {
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-1: (0.5e6, 200e6),
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-2: (0.5e6, 333e6),
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-3: (0.5e6, 375e6),
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}[speedgrade]
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self.vco_freq_range = {
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-1: (5e6, 1e16),
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-2: (5e6, 1e16),
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-3: (5e6, 1e16),
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}[speedgrade]
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def do_finalize(self):
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XilinxClocking.do_finalize(self)
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config = self.compute_config()
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clk, f, p, m = sorted(self.clkouts.items())[0][1]
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self.params.update(
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p_CLKFX_MULTIPLY = config["clkfbout_mult"],
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p_CLKFX_DIVIDE = config["clkout0_divide"] * config["divclk_divide"],
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p_SPREAD_SPECTRUM = "NONE",
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p_CLKIN_PERIOD = 1e9/self.clkin_freq,
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i_CLKIN = self.clkin,
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i_RST = self.reset,
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i_FREEZEDCM = 0,
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o_CLKFX = clk,
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o_LOCKED = self.locked,
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)
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self.specials += Instance("DCM_CLKGEN", **self.params)
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# Xilinx / 7-Series --------------------------------------------------------------------------------
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class S7PLL(XilinxClocking):
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nclkouts_max = 6
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clkin_freq_range = (19e6, 800e6)
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("S7PLL")
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self.logger.info("Creating S7PLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 56+1)
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self.vco_freq_range = {
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-1: (800e6, 1600e6),
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-2: (800e6, 1866e6),
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-3: (800e6, 2133e6),
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}[speedgrade]
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def do_finalize(self):
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XilinxClocking.do_finalize(self)
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config = self.compute_config()
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pll_fb = Signal()
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self.params.update(
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLLE2_ADV", **self.params)
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class S7MMCM(XilinxClocking):
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nclkouts_max = 7
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clkout0_divide_range = (1, (128 + 1/8), 1/8) # Fractional Divide available on CLKOUT0
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("S7MMCM")
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self.logger.info("Creating S7MMCM, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 106+1)
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self.clkin_freq_range = {
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-1: (10e6, 800e6),
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-2: (10e6, 933e6),
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-3: (10e6, 1066e6),
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}[speedgrade]
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self.vco_freq_range = {
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-1: (600e6, 1200e6),
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-2: (600e6, 1440e6),
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-3: (600e6, 1600e6),
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}[speedgrade]
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def do_finalize(self):
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XilinxClocking.do_finalize(self)
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config = self.compute_config()
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mmcm_fb = Signal()
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self.params.update(
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p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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if n == 0:
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self.params["p_CLKOUT{}_DIVIDE_F".format(n)] = config["clkout{}_divide".format(n)]
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else:
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("MMCME2_ADV", **self.params)
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class S7IDELAYCTRL(Module):
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def __init__(self, cd, reset_cycles=16):
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reset_counter = Signal(log2_int(reset_cycles), reset=reset_cycles - 1)
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ic_reset = Signal(reset=1)
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sync = getattr(self.sync, cd.name)
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sync += \
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If(reset_counter != 0,
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reset_counter.eq(reset_counter - 1)
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).Else(
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ic_reset.eq(0)
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)
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self.specials += Instance("IDELAYCTRL", i_REFCLK=cd.clk, i_RST=ic_reset)
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# Xilinx / Ultrascale ------------------------------------------------------------------------------
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# TODO:
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# - use Ultrascale primitives instead of 7-Series' ones. (Vivado recognize and convert them).
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class USPLL(XilinxClocking):
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nclkouts_max = 6
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("USPLL")
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self.logger.info("Creating USPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 56+1)
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self.clkin_freq_range = {
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-1: (70e6, 800e6),
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-2: (70e6, 933e6),
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-3: (70e6, 1066e6),
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}[speedgrade]
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self.vco_freq_range = {
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-1: (600e6, 1200e6),
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-2: (600e6, 1335e6),
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-3: (600e6, 1335e6),
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}[speedgrade]
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def do_finalize(self):
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XilinxClocking.do_finalize(self)
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config = self.compute_config()
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pll_fb = Signal()
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self.params.update(
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p_STARTUP_WAIT="FALSE", o_LOCKED=self.locked, i_RST=self.reset,
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# VCO
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p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
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p_CLKFBOUT_MULT=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
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i_CLKIN1=self.clkin, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
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)
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for n, (clk, f, p, m) in sorted(self.clkouts.items()):
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self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
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self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
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self.params["o_CLKOUT{}".format(n)] = clk
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self.specials += Instance("PLLE2_ADV", **self.params)
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class USMMCM(XilinxClocking):
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nclkouts_max = 7
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def __init__(self, speedgrade=-1):
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self.logger = logging.getLogger("USMMCM")
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self.logger.info("Creating UMMCM, {}.".format(colorer("speedgrade {}".format(speedgrade))))
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XilinxClocking.__init__(self)
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self.divclk_divide_range = (1, 106+1)
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self.clkin_freq_range = {
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-1: (10e6, 800e6),
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-2: (10e6, 933e6),
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-3: (10e6, 1066e6),
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}[speedgrade]
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self.vco_freq_range = {
|
|
-1: (600e6, 1200e6),
|
|
-2: (600e6, 1440e6),
|
|
-3: (600e6, 1600e6),
|
|
}[speedgrade]
|
|
|
|
def do_finalize(self):
|
|
XilinxClocking.do_finalize(self)
|
|
config = self.compute_config()
|
|
mmcm_fb = Signal()
|
|
self.params.update(
|
|
p_BANDWIDTH="OPTIMIZED", o_LOCKED=self.locked, i_RST=self.reset,
|
|
|
|
# VCO
|
|
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=1e9/self.clkin_freq,
|
|
p_CLKFBOUT_MULT_F=config["clkfbout_mult"], p_DIVCLK_DIVIDE=config["divclk_divide"],
|
|
i_CLKIN1=self.clkin, i_CLKFBIN=mmcm_fb, o_CLKFBOUT=mmcm_fb,
|
|
)
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
if n == 0:
|
|
self.params["p_CLKOUT{}_DIVIDE_F".format(n)] = config["clkout{}_divide".format(n)]
|
|
else:
|
|
self.params["p_CLKOUT{}_DIVIDE".format(n)] = config["clkout{}_divide".format(n)]
|
|
self.params["p_CLKOUT{}_PHASE".format(n)] = config["clkout{}_phase".format(n)]
|
|
self.params["o_CLKOUT{}".format(n)] = clk
|
|
self.specials += Instance("MMCME2_ADV", **self.params)
|
|
|
|
|
|
class USIDELAYCTRL(Module):
|
|
def __init__(self, cd_ref, cd_sys, reset_cycles=64, ready_cycles=64):
|
|
cd_sys.rst.reset = 1
|
|
self.clock_domains.cd_ic = ClockDomain()
|
|
ic_reset_counter = Signal(max=reset_cycles, reset=reset_cycles-1)
|
|
ic_reset = Signal(reset=1)
|
|
cd_ref_sync = getattr(self.sync, cd_ref.name)
|
|
cd_ref_sync += [
|
|
If(ic_reset_counter != 0,
|
|
ic_reset_counter.eq(ic_reset_counter - 1)
|
|
).Else(
|
|
ic_reset.eq(0)
|
|
)
|
|
]
|
|
ic_ready_counter = Signal(max=ready_cycles, reset=ready_cycles-1)
|
|
ic_ready = Signal()
|
|
self.comb += self.cd_ic.clk.eq(cd_sys.clk)
|
|
self.sync.ic += [
|
|
If(ic_ready,
|
|
If(ic_ready_counter != 0,
|
|
ic_ready_counter.eq(ic_ready_counter - 1)
|
|
).Else(
|
|
cd_sys.rst.eq(0)
|
|
)
|
|
)
|
|
]
|
|
self.specials += [
|
|
Instance("IDELAYCTRL",
|
|
p_SIM_DEVICE = "ULTRASCALE",
|
|
i_REFCLK = cd_ref.clk,
|
|
i_RST = ic_reset,
|
|
o_RDY = ic_ready),
|
|
AsyncResetSynchronizer(self.cd_ic, ic_reset)
|
|
]
|
|
|
|
# Lattice / iCE40 ----------------------------------------------------------------------------------
|
|
|
|
# TODO:
|
|
# - add phase support.
|
|
# - add support for GENCLK_HALF to be able to generate clock down to 8MHz.
|
|
|
|
class iCE40PLL(Module):
|
|
nclkouts_max = 1
|
|
divr_range = (0, 16)
|
|
divf_range = (0, 128)
|
|
divq_range = (0, 7)
|
|
clki_freq_range = ( 10e6, 133e9)
|
|
clko_freq_range = ( 16e6, 275e9)
|
|
vco_freq_range = (533e6, 1066e6)
|
|
|
|
def __init__(self, primitive="SB_PLL40_CORE"):
|
|
assert primitive in ["SB_PLL40_CORE", "SB_PLL40_PAD"]
|
|
self.logger = logging.getLogger("iCE40PLL")
|
|
self.logger.info("Creating iCE40PLL, {} primitive.".format(colorer(primitive)))
|
|
self.primitive = primitive
|
|
self.reset = Signal()
|
|
self.locked = Signal()
|
|
self.clkin_freq = None
|
|
self.vcxo_freq = None
|
|
self.nclkouts = 0
|
|
self.clkouts = {}
|
|
self.config = {}
|
|
self.params = {}
|
|
|
|
def register_clkin(self, clkin, freq):
|
|
(clki_freq_min, clki_freq_max) = self.clki_freq_range
|
|
assert freq >= clki_freq_min
|
|
assert freq <= clki_freq_max
|
|
self.clkin = Signal()
|
|
if isinstance(clkin, (Signal, ClockSignal)):
|
|
self.comb += self.clkin.eq(clkin)
|
|
else:
|
|
raise ValueError
|
|
self.clkin_freq = freq
|
|
register_clkin_log(self.logger, clkin, freq)
|
|
|
|
def create_clkout(self, cd, freq, margin=1e-2):
|
|
(clko_freq_min, clko_freq_max) = self.clko_freq_range
|
|
assert freq >= clko_freq_min
|
|
assert freq <= clko_freq_max
|
|
assert self.nclkouts < self.nclkouts_max
|
|
clkout = Signal()
|
|
self.clkouts[self.nclkouts] = (clkout, freq, 0, margin)
|
|
self.comb += cd.clk.eq(clkout)
|
|
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
|
|
self.nclkouts += 1
|
|
|
|
def compute_config(self):
|
|
config = {}
|
|
for divr in range(*self.divr_range):
|
|
for divf in range(*self.divf_range):
|
|
all_valid = True
|
|
vco_freq = self.clkin_freq/(divr + 1)*(divf + 1)
|
|
(vco_freq_min, vco_freq_max) = self.vco_freq_range
|
|
if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
valid = False
|
|
for divq in range(*self.divq_range):
|
|
clk_freq = vco_freq/(2**divq)
|
|
if abs(clk_freq - f) <= f*m:
|
|
config["clkout_freq"] = clk_freq
|
|
config["divq"] = divq
|
|
valid = True
|
|
break
|
|
if not valid:
|
|
all_valid = False
|
|
else:
|
|
all_valid = False
|
|
if all_valid:
|
|
config["vco"] = vco_freq
|
|
config["divr"] = divr
|
|
config["divf"] = divf
|
|
compute_config_log(self.logger, config)
|
|
return config
|
|
raise ValueError("No PLL config found")
|
|
|
|
def do_finalize(self):
|
|
config = self.compute_config()
|
|
clkfb = Signal()
|
|
for f, v in [(17e6, 1), (26e6, 2), (44e6, 3), (66e6, 4), (101e6, 5), (133e6, 6)]:
|
|
pfd_freq = self.clkin_freq/(config["divr"] + 1)
|
|
if pfd_freq < f:
|
|
filter_range = v
|
|
break
|
|
self.params.update(
|
|
p_FEEDBACK_PATH = "SIMPLE",
|
|
p_FILTER_RANGE = filter_range,
|
|
i_RESETB = ~self.reset,
|
|
o_LOCK = self.locked,
|
|
)
|
|
if self.primitive == "SB_PLL40_CORE":
|
|
self.params.update(i_REFERENCECLK=self.clkin)
|
|
if self.primitive == "SB_PLL40_PAD":
|
|
self.params.update(i_PACKAGEPIN=self.clkin)
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
self.params["p_DIVR"] = config["divr"]
|
|
self.params["p_DIVF"] = config["divf"]
|
|
self.params["p_DIVQ"] = config["divq"]
|
|
self.params["o_PLLOUTGLOBAL"] = clk
|
|
self.specials += Instance(self.primitive, **self.params)
|
|
|
|
# Lattice / ECP5 -----------------------------------------------------------------------------------
|
|
|
|
class ECP5PLL(Module):
|
|
nclkouts_max = 3
|
|
clki_div_range = (1, 128+1)
|
|
clkfb_div_range = (1, 128+1)
|
|
clko_div_range = (1, 128+1)
|
|
clki_freq_range = ( 8e6, 400e6)
|
|
clko_freq_range = (3.125e6, 400e6)
|
|
vco_freq_range = ( 400e6, 800e6)
|
|
|
|
def __init__(self):
|
|
self.logger = logging.getLogger("ECP5PLL")
|
|
self.logger.info("Creating ECP5PLL.")
|
|
self.reset = Signal()
|
|
self.locked = Signal()
|
|
self.clkin_freq = None
|
|
self.vcxo_freq = None
|
|
self.nclkouts = 0
|
|
self.clkouts = {}
|
|
self.config = {}
|
|
self.params = {}
|
|
|
|
def register_clkin(self, clkin, freq):
|
|
(clki_freq_min, clki_freq_max) = self.clki_freq_range
|
|
assert freq >= clki_freq_min
|
|
assert freq <= clki_freq_max
|
|
self.clkin = Signal()
|
|
if isinstance(clkin, (Signal, ClockSignal)):
|
|
self.comb += self.clkin.eq(clkin)
|
|
else:
|
|
raise ValueError
|
|
self.clkin_freq = freq
|
|
register_clkin_log(self.logger, clkin, freq)
|
|
|
|
def create_clkout(self, cd, freq, phase=0, margin=1e-2):
|
|
(clko_freq_min, clko_freq_max) = self.clko_freq_range
|
|
assert freq >= clko_freq_min
|
|
assert freq <= clko_freq_max
|
|
assert self.nclkouts < self.nclkouts_max
|
|
clkout = Signal()
|
|
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
|
|
self.comb += cd.clk.eq(clkout)
|
|
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
|
|
self.nclkouts += 1
|
|
|
|
def compute_config(self):
|
|
config = {}
|
|
for clki_div in range(*self.clki_div_range):
|
|
config["clki_div"] = clki_div
|
|
for clkfb_div in range(*self.clkfb_div_range):
|
|
all_valid = True
|
|
vco_freq = self.clkin_freq/clki_div*clkfb_div*1 # clkos3_div=1
|
|
(vco_freq_min, vco_freq_max) = self.vco_freq_range
|
|
if vco_freq >= vco_freq_min and vco_freq <= vco_freq_max:
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
valid = False
|
|
for d in range(*self.clko_div_range):
|
|
clk_freq = vco_freq/d
|
|
if abs(clk_freq - f) <= f*m:
|
|
config["clko{}_freq".format(n)] = clk_freq
|
|
config["clko{}_div".format(n)] = d
|
|
config["clko{}_phase".format(n)] = p
|
|
valid = True
|
|
break
|
|
if not valid:
|
|
all_valid = False
|
|
else:
|
|
all_valid = False
|
|
if all_valid:
|
|
config["vco"] = vco_freq
|
|
config["clkfb_div"] = clkfb_div
|
|
compute_config_log(self.logger, config)
|
|
return config
|
|
raise ValueError("No PLL config found")
|
|
|
|
def do_finalize(self):
|
|
config = self.compute_config()
|
|
clkfb = Signal()
|
|
self.params.update(
|
|
attr=[
|
|
("FREQUENCY_PIN_CLKI", str(self.clkin_freq/1e6)),
|
|
("ICP_CURRENT", "6"),
|
|
("LPF_RESISTOR", "16"),
|
|
("MFG_ENABLE_FILTEROPAMP", "1"),
|
|
("MFG_GMCREF_SEL", "2")],
|
|
i_RST = self.reset,
|
|
i_CLKI = self.clkin,
|
|
o_LOCK = self.locked,
|
|
p_FEEDBK_PATH = "INT_OS3", # CLKOS3 reserved for feedback with div=1.
|
|
p_CLKOS3_ENABLE = "ENABLED",
|
|
p_CLKOS3_DIV = 1,
|
|
p_CLKFB_DIV = config["clkfb_div"],
|
|
p_CLKI_DIV = config["clki_div"],
|
|
)
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
n_to_l = {0: "P", 1: "S", 2: "S2"}
|
|
div = config["clko{}_div".format(n)]
|
|
cphase = int(p*(div + 1)/360 + div)
|
|
self.params["p_CLKO{}_ENABLE".format(n_to_l[n])] = "ENABLED"
|
|
self.params["p_CLKO{}_DIV".format(n_to_l[n])] = div
|
|
self.params["p_CLKO{}_FPHASE".format(n_to_l[n])] = 0
|
|
self.params["p_CLKO{}_CPHASE".format(n_to_l[n])] = cphase
|
|
self.params["o_CLKO{}".format(n_to_l[n])] = clk
|
|
self.specials += Instance("EHXPLLL", **self.params)
|
|
|
|
# Intel / Generic ---------------------------------------------------------------------------------
|
|
|
|
class IntelClocking(Module, AutoCSR):
|
|
def __init__(self, vco_margin=0):
|
|
self.vco_margin = vco_margin
|
|
self.reset = Signal()
|
|
self.locked = Signal()
|
|
self.clkin_freq = None
|
|
self.vcxo_freq = None
|
|
self.nclkouts = 0
|
|
self.clkouts = {}
|
|
self.config = {}
|
|
self.params = {}
|
|
|
|
def register_clkin(self, clkin, freq):
|
|
self.clkin = Signal()
|
|
if isinstance(clkin, (Signal, ClockSignal)):
|
|
self.comb += self.clkin.eq(clkin)
|
|
elif isinstance(clkin, Record):
|
|
self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
|
|
else:
|
|
raise ValueError
|
|
self.clkin_freq = freq
|
|
register_clkin_log(self.logger, clkin, freq)
|
|
|
|
def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
|
|
assert self.nclkouts < self.nclkouts_max
|
|
clkout = Signal()
|
|
self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
|
|
if with_reset:
|
|
self.specials += AsyncResetSynchronizer(cd, ~self.locked | self.reset)
|
|
self.comb += cd.clk.eq(clkout)
|
|
create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
|
|
self.nclkouts += 1
|
|
|
|
def compute_config(self):
|
|
config = {}
|
|
for n in range(*self.n_div_range):
|
|
config["n"] = n
|
|
for m in reversed(range(*self.m_div_range)):
|
|
all_valid = True
|
|
vco_freq = self.clkin_freq*m/n
|
|
(vco_freq_min, vco_freq_max) = self.vco_freq_range
|
|
if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
|
|
vco_freq <= vco_freq_max*(1 - self.vco_margin)):
|
|
for _n, (clk, f, p, _m) in sorted(self.clkouts.items()):
|
|
valid = False
|
|
for c in clkdiv_range(*self.c_div_range):
|
|
clk_freq = vco_freq/c
|
|
if abs(clk_freq - f) <= f*_m:
|
|
config["clk{}_freq".format(_n)] = clk_freq
|
|
config["clk{}_divide".format(_n)] = c
|
|
config["clk{}_phase".format(_n)] = p
|
|
valid = True
|
|
break
|
|
if valid:
|
|
break
|
|
if not valid:
|
|
all_valid = False
|
|
else:
|
|
all_valid = False
|
|
if all_valid:
|
|
config["vco"] = vco_freq
|
|
config["m"] = m
|
|
compute_config_log(self.logger, config)
|
|
return config
|
|
raise ValueError("No PLL config found")
|
|
|
|
def do_finalize(self):
|
|
assert hasattr(self, "clkin")
|
|
config = self.compute_config()
|
|
clks = Signal(self.nclkouts)
|
|
self.params.update(
|
|
p_BANDWIDTH_TYPE = "AUTO",
|
|
p_COMPENSATE_CLOCK = "CLK0",
|
|
p_INCLK0_INPUT_FREQUENCY = int(1e12/self.clkin_freq),
|
|
p_OPERATION_MODE = "NORMAL",
|
|
i_INCLK = self.clkin,
|
|
o_CLK = clks,
|
|
i_ARESET = 0,
|
|
i_CLKENA = 2**self.nclkouts_max - 1,
|
|
i_EXTCLKENA = 0xf,
|
|
i_FBIN = 1,
|
|
i_PFDENA = 1,
|
|
i_PLLENA = 1,
|
|
o_LOCKED = self.locked,
|
|
)
|
|
for n, (clk, f, p, m) in sorted(self.clkouts.items()):
|
|
clk_phase_ps = int((1e12/config["clk{}_freq".format(n)])*config["clk{}_phase".format(n)]/360)
|
|
self.params["p_CLK{}_DIVIDE_BY".format(n)] = config["clk{}_divide".format(n)]
|
|
self.params["p_CLK{}_DUTY_CYCLE".format(n)] = 50
|
|
self.params["p_CLK{}_MULTIPLY_BY".format(n)] = config["m"]
|
|
self.params["p_CLK{}_PHASE_SHIFT".format(n)] = clk_phase_ps
|
|
self.comb += clk.eq(clks[n])
|
|
self.specials += Instance("ALTPLL", **self.params)
|
|
|
|
# Intel / CycloneIV -------------------------------------------------------------------------------
|
|
|
|
class CycloneIVPLL(IntelClocking):
|
|
nclkouts_max = 5
|
|
n_div_range = (1, 512+1)
|
|
m_div_range = (1, 512+1)
|
|
c_div_range = (1, 512+1)
|
|
vco_freq_range = (600e6, 1300e6)
|
|
def __init__(self, speedgrade="-6"):
|
|
self.logger = logging.getLogger("CycloneIVPLL")
|
|
self.logger.info("Creating CycloneIVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
|
|
IntelClocking.__init__(self)
|
|
self.clkin_freq_range = {
|
|
"-6" : (5e6, 472.5e6),
|
|
"-7" : (5e6, 472.5e6),
|
|
"-8" : (5e6, 472.5e6),
|
|
"-8L": (5e6, 362e6),
|
|
"-9L": (5e6, 256e6),
|
|
}[speedgrade]
|
|
self.clko_freq_range = {
|
|
"-6" : (0e6, 472.5e6),
|
|
"-7" : (0e6, 450e6),
|
|
"-8" : (0e6, 402.5e6),
|
|
"-8L": (0e6, 362e6),
|
|
"-9L": (0e6, 265e6),
|
|
}[speedgrade]
|
|
|
|
# Intel / CycloneV --------------------------------------------------------------------------------
|
|
|
|
class CycloneVPLL(IntelClocking):
|
|
nclkouts_max = 5
|
|
n_div_range = (1, 512+1)
|
|
m_div_range = (1, 512+1)
|
|
c_div_range = (1, 512+1)
|
|
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
|
|
clkfin_pfd_freq_range = (50e6, 160e6) # FIXME: use
|
|
def __init__(self, speedgrade="-C6"):
|
|
self.logger = logging.getLogger("CycloneVPLL")
|
|
self.logger.info("Creating CycloneVPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
|
|
IntelClocking.__init__(self)
|
|
self.clkin_freq_range = {
|
|
"-C6" : (5e6, 670e6),
|
|
"-C7" : (5e6, 622e6),
|
|
"-I7" : (5e6, 622e6),
|
|
"-C8" : (5e6, 622e6),
|
|
"-A7" : (5e6, 500e6),
|
|
}[speedgrade]
|
|
self.vco_freq_range = {
|
|
"-C6" : (600e6, 1600e6),
|
|
"-C7" : (600e6, 1600e6),
|
|
"-I7" : (600e6, 1600e6),
|
|
"-C8" : (600e6, 1300e6),
|
|
"-A7" : (600e6, 1300e6),
|
|
}[speedgrade]
|
|
self.clko_freq_range = {
|
|
"-C6" : (0e6, 550e6),
|
|
"-C7" : (0e6, 550e6),
|
|
"-I7" : (0e6, 550e6),
|
|
"-C8" : (0e6, 460e6),
|
|
"-A7" : (0e6, 460e6),
|
|
}[speedgrade]
|
|
|
|
# Intel / Cyclone10LP ------------------------------------------------------------------------------
|
|
|
|
class Cyclone10LPPLL(IntelClocking):
|
|
nclkouts_max = 5
|
|
n_div_range = (1, 512+1)
|
|
m_div_range = (1, 512+1)
|
|
c_div_range = (1, 512+1)
|
|
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
|
|
vco_freq_range = (600e6, 1300e6)
|
|
def __init__(self, speedgrade="-C6"):
|
|
self.logger = logging.getLogger("Cyclone10LPPLL")
|
|
self.logger.info("Creating Cyclone10LPPLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
|
|
IntelClocking.__init__(self)
|
|
self.clkin_freq_range = {
|
|
"-C6" : (5e6, 472.5e6),
|
|
"-C8" : (5e6, 472.5e6),
|
|
"-I7" : (5e6, 472.5e6),
|
|
"-A7" : (5e6, 472.5e6),
|
|
"-I8" : (5e6, 362e6),
|
|
}[speedgrade]
|
|
self.clko_freq_range = {
|
|
"-C6" : (0e6, 472.5e6),
|
|
"-C8" : (0e6, 402.5e6),
|
|
"-I7" : (0e6, 450e6),
|
|
"-A7" : (0e6, 450e6),
|
|
"-I8" : (0e6, 362e6),
|
|
}[speedgrade]
|
|
|
|
# Intel / Max10 ------------------------------------------------------------------------------------
|
|
|
|
class Max10PLL(IntelClocking):
|
|
nclkouts_max = 5
|
|
n_div_range = (1, 512+1)
|
|
m_div_range = (1, 512+1)
|
|
c_div_range = (1, 512+1)
|
|
clkin_freq_range = (5e6, 472.5e6)
|
|
clkin_pfd_freq_range = (5e6, 325e6) # FIXME: use
|
|
vco_freq_range = (600e6, 1300e6)
|
|
def __init__(self, speedgrade="-6"):
|
|
self.logger = logging.getLogger("Max10PLL")
|
|
self.logger.info("Creating Max10PLL, {}.".format(colorer("speedgrade {}".format(speedgrade))))
|
|
IntelClocking.__init__(self)
|
|
self.clko_freq_range = {
|
|
"-6" : (0e6, 472.5e6),
|
|
"-7" : (0e6, 450e6),
|
|
"-8" : (0e6, 402.5e6),
|
|
}[speedgrade]
|