litex/litex
Florent Kermarrec 285bb96278 cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default.
Dynamic baudrate is rarely used and enabling it has a non negligeable cost (~100LCs).
2021-02-16 20:00:43 +01:00
..
build build/xilinx/symbiflow: fix bitstream_device select 2021-02-08 15:38:30 +01:00
gen gen/fhdl/verilog: improve clock domain error reporting. 2020-11-10 13:27:29 +01:00
soc cores/uart/RS232PHY: add with_dynamic_baudrate parameter and disable it by default. 2021-02-16 20:00:43 +01:00
tools litex_term: support Intel/Altera nios2-terminal 2021-02-08 11:42:37 +07:00
__init__.py revert get_data_mod change (Vexrisv SMP repo has been renamed to pythondata-cpu-vexriscv_smp). 2020-11-05 19:55:18 +01:00