litex/litex/soc
2019-08-15 09:27:33 +02:00
..
cores cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) 2019-08-14 07:35:45 +02:00
integration cpu_interface: add json csr map export, simplify csv csr map export using json 2019-08-15 09:27:33 +02:00
interconnect [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat 2019-08-14 11:30:39 +02:00
software bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) 2019-08-14 19:09:58 +02:00
__init__.py litex: reorganize things, first work working version 2015-11-07 17:48:55 +01:00