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28d04ec300
litex
/
misoclib
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soc
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Florent Kermarrec
28d04ec300
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00
..
__init__.py
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00
cpuif.py
cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
2015-03-02 16:52:17 +01:00
sdram.py
soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
2015-03-14 00:49:19 +01:00